SNVSCS6A March   2026  – August 2026 TPS7H1301-SP , TPS7H1302-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Quality Conformance Inspection
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable
      2. 9.3.2  Charge Pump
        1. 9.3.2.1 Charge Pump Operation
        2. 9.3.2.2 Foldback Switching
      3. 9.3.3  Startup
      4. 9.3.4  Power Good
      5. 9.3.5  Output Voltage
      6. 9.3.6  Dropout
      7. 9.3.7  Output Voltage Accuracy
      8. 9.3.8  Output Noise
      9. 9.3.9  Power Supply Rejection Ratio
      10. 9.3.10 Stability
        1. 9.3.10.1 Stability of the TPS7H1301
        2. 9.3.10.2 Stability of the TPS7H1302
      11. 9.3.11 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable Disable
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application TPS7H1301
      1. 10.2.1 Design Requirements TPS7H1301
      2. 10.2.2 Detailed Design Procedure TPS7H1301
        1. 10.2.2.1 Capacitor Selection
          1. 10.2.2.1.1 Input Capacitor (CIN) Selection
          2. 10.2.2.1.2 CFLY TPS7H1301
          3. 10.2.2.1.3 CPOUT Capacitor TPS7H1301
          4. 10.2.2.1.4 Bypass Capacitors
          5. 10.2.2.1.5 Output Capacitor
        2. 10.2.2.2 Charge Pump Output Resistance
        3. 10.2.2.3 Configuring LDO Output
        4. 10.2.2.4 Output Noise
        5. 10.2.2.5 PSRR Design Implications
        6. 10.2.2.6 Stability Design Considerations
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application TPS7H1301 Parallel Operation
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure Parallel TPS7H1301
        1. 10.3.2.1 Parallel Ballast Resistor
      3. 10.3.3 Application Performance Plots
    4. 10.4 Typical Application TPS7H1302
      1. 10.4.1 Design Requirements TPS7H1302
      2. 10.4.2 Detailed Design Procedure TPS7H1302
        1. 10.4.2.1 Capacitor Selection TPS7H1302
        2. 10.4.2.2 CFLY Capacitor TPS7H1302
        3. 10.4.2.3 CPOUT Capacitor TPS7H1302
        4. 10.4.2.4 Stability TPS7H1302
      3. 10.4.3 TPS7H1302 Application Performance Plots
    5. 10.5 TPS7H1302 Low Noise Configuration
      1. 10.5.1 Design Requirements TPS7H1302 Low Noise
      2. 10.5.2 Application Performance Plots
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 13.1 Tube Information
    3.     88

10.2.2.6 Stability Design Considerations

TPS7H1301-SP TPS7H1302-SP Simplified Pole Zero Analysis Figure 10-2 Simplified Pole Zero Analysis

The stability of the LDO is influenced primarily by the dominant load pole and zero for the output capacitor (PCOUT, ZCOUT) and the internal compensation network (PCOMP_INT, ZCOMP_INT). Figure 10-2 illustrates where the pole and zero of the output capacitor and the internal compensation pole and zero of the LDO are located.

The pole and zero of the output capacitor are calculated using Equation 22 and Equation 23:

Equation 22. P C O U T = 1 2 π × R L O A D × C O U T
Equation 23. Z C O U T = 1 2 π × E S R C O U T × C O U T

Applying Equation 22 and Equation 23 results in the following location of the respective pole and zero:

Equation 24. P C O U T = 1 2 π × 7.2 Ω × 22 µ F = 1003 H z
Equation 25. Z C O U T = 1 2 π × 5 m Ω × 22 µ F = 1.446 M H z

The internal compensation network pole and zero are calculated using Equation 26 and Equation 27:

Equation 26. P C O M P _ I N T = C C O M P _ I N T + C O T A 2 π × R C O M P × C C O M P _ I N T × C O T A
Equation 27. Z C O M P _ I N T = 1 2 π × R C O M P × C C O M P _ I N T

COTA is the error amplifier's output capacitance; which is specified by design to be 20pf.

Applying Equation 26 and Equation 27 results in the following location of the respective pole and zero:

Equation 28. P C O M P _ I N T = 400 p F + 20 p F 2 π × 30 k Ω × 400 p F × 20 p F = 253 k H z
Equation 29. Z C O M P _ I N T = 1 2 π × 30 k Ω × 400 p F = 13.3 k H z

When applying an external compensation network utilizing the STAB pin utilize Equation 30 and Equation 31:

Equation 30. P C O M P _ E X T = C C O M P _ I N T \ \ C C O M P _ E X T + C O T A 2 π × R C O M P _ I N T \ \ R C O M P _ E X T × C C O M P _ I N T \ \ C C O M P _ E X T × C g
Equation 31. Z C O M P _ E X T = 1 2 π × R C O M P _ I N T \ \ R C O M P _ E X T × C C O M P _ I N T \ \ C C O M P _ E X T