SNVSCT6 July   2026 LM72630-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN/UVLO)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage and Output Voltage Slew Rate
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable OVP
      11. 7.3.11 Programmable ILIM
      12. 7.3.12 IOUT Monitor
      13. 7.3.13 Cable Drop Compensation
      14. 7.3.14 Slope Compensation
      15. 7.3.15 Shunt Current Sensing
      16. 7.3.16 Hiccup Mode Current Limiting
      17. 7.3.17 Device Configuration (CNFG)
      18. 7.3.18 Pulse Frequency Modulation (PFM) / Synchronization
      19. 7.3.19 Out-of-Audio Operation
      20. 7.3.20 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. 8 LM72630-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
      3. 9.1.3 Maximum Ambient Temperature
        1. 9.1.3.1 Derating Curves
    2. 9.2 Typical Application
      1. 9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Compensation Components
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
9.2.1.2.3 Current-Sense Resistance
  1. Calculate the current-sense resistance based on a maximum peak current capability of at least 20% – 25% higher than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients. Calculate the current sense resistance using Equation 31.
    Equation 31. R S = V C S ( T H ) 1.2 × I L O P K   = 40 m V 1.2 × 3 . 812   =   8.7 m Ω

    where

    VCS(TH) is the 40mV current limit threshold.

  2. Select a standard resistance value of 8mΩ for the shunt. A 0508 footprint component with wide aspect ratio termination design provides 1W power rating, low parasitic series inductance, and compact PCB layout. Carefully observe the Layout Guidelines to make sure that noise and DC errors do not corrupt the differential current-sense voltages measured at the ISNS+ and VOUTS pins.
  3. Place the shunt resistor close to the inductor.
  4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the device.
  5. The ISNS-to-output propagation delay (related to the current limit comparator, internal logic and power MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For a total propagation delay tISNS(delay) of 85ns, use Equation 32 to calculate the worst-case peak inductor current with the output shorted.
    Equation 32. I L O P K S C   =   V C S ( T H ) R S + V I N ( m a x ) × t I S N S ( d e l a y ) L O   = 40 m V 8 m Ω + 70 V × 85 n s 22 µ H = 5 . 27 A    
  6. Based on this result, select an inductor with saturation current greater than 8A across the full operating temperature range.