SNVSCT6 July   2026 LM72630-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Related Products
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN/UVLO)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage and Output Voltage Slew Rate
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable OVP
      11. 7.3.11 Programmable ILIM
      12. 7.3.12 IOUT Monitor
      13. 7.3.13 Cable Drop Compensation
      14. 7.3.14 Slope Compensation
      15. 7.3.15 Shunt Current Sensing
      16. 7.3.16 Hiccup Mode Current Limiting
      17. 7.3.17 Device Configuration (CNFG)
      18. 7.3.18 Pulse Frequency Modulation (PFM) / Synchronization
      19. 7.3.19 Out-of-Audio Operation
      20. 7.3.20 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. LM72630-Q1 Registers
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
      3. 9.1.3 Maximum Ambient Temperature
        1. 9.1.3.1 Derating Curves
    2. 9.2 Typical Application
      1. 9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Compensation Components
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Pulse Frequency Modulation (PFM) / Synchronization

The LM72630-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation (DEM), the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss during light load operation. Note configuring the device for DEM has an effect of slower response to load transients during light load operation.

The diode emulation feature is configured with the PFM / SYNCIN pin or OVERRIDE_PFM and MODE bits. To enable diode emulation and thus achieve discontinuous conduction mode (DCM) operation at light loads, connect PFM / SYNCIN to VDDA or set OVERRIDE_PFM and MODE bits. If forced pulse-width modulation (FPWM) or continuous conduction mode (CCM) operation is desired, tie PFM / SYNCIN to AGND or set OVERRIDE_PFM bit and reset MODE bit. Note that diode emulation is automatically engaged to prevent reverse current flow during a prebias start-up in PFM. During start-up, when the output voltage approaches the regulation set point a gradual change from DCM to CCM occurs, preventing the output voltage overshoot. Changing the mode of operation dynamically is possible, however, the rate of change must be < 10Hz. The time to transition from PFM to FPWM operation is dependent on the output load current. In a typical application, the transition from PFM to FPWM operation occurs in less than 1ms if the output current is greater than 100mA. Similarly, for the output currents of around 1mA, the transition generally occurs in tens of milliseconds. Enable the output active discharge feature during the transition between PFM and FPWM to reduce the transition time. Select 24mA, 48mA, or 72mA active discharge strength using ACTIVE_DISCHARGE_STRENGTH bits.

If forced pulse-width modulation (FPWM) or continuous conduction mode (CCM) operation is desired, tie PFM / SYNCIN to AGND. Note that the LM72630-Q1 transitions from PFM to FPWM mode whenever LM72630-Q1 is reset. The time to transition to FPWM operation is dependent on the output load current. In a typical application, the transition from PFM to FPWM operation occurs in less than 1ms if the output current is greater than 100mA. Similarly, for the output currents of around 1mA, the transition generally occurs in tens of milliseconds.

To synchronize the LM72630-Q1 to an external source, apply a logic-level clock (greater than 2V) to the PFM / SYNCIN pin. The LM72630-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.2MHz. Never synchronize the device to an external clock with frequency of < 100kHz. Under low VIN conditions when the minimum off-time is reached, the synchronization signal is ignored, allowing the switching frequency to be reduced to maintain output voltage regulation.

When in FPWM mode, the time for the LM72630-Q1 to be synchronized to an external clock frequency is approximately 100μs. If an external clock is applied after start-up while operating in PFM mode, the time to synchronize the switching frequency is dependent on the output load current. In a typical application, switch synchronization and FPWM operation occurs in less than 1ms if the output current exceeds 100mA. Similarly, for the output currents of 1mA or more synchronization generally occurs in tens of milliseconds. Enable the output active discharge feature during the transition between PFM and FPWM to reduce the synchronization time.