SNVSCU1A July 2025 – November 2025 TPSM65630
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| FB | 1 | A | Feedback configuration pin. Connect to GND to configure 3.3V fixed output voltage. Connect to VCC to configure 5V fixed output voltage. Connect this pin to a feedback divider for adjustable output options. The regulation threshold is 0.8V. |
| VOUT | 2 | O | Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and connect external output capacitors between the pin and PGND. |
| MODE / SYNC | 3 | I/O | Mode and synchronization input pin. Connect to GND, or drive the pin low to operate in AUTO mode. Connect to VCC, or drive the pin high, or send a synchronization clock signal to operate in FPWM mode. When synchronized to an external clock, use the RT pin to set the internal frequency close to the synchronized frequency. |
| RT | 4 | I/O | Switching frequency programming pin. Connect this pin to VCC for 400kHz operation, or to GND for 2.2MHz operation. Connect this pin to ground through a resistor to set the switching frequency between 300kHz and 2200kHz. Do not float. |
| EN / UVLO | 5 | P | Precision enable pin. High = ON, Low = OFF. This pin can be directly connected to VIN. The precision threshold on this input enables use as an adjustable UVLO. Do not float. |
| NC | 6 | — | No connect pin. Leave floating. |
| NC | 7 | — | No connect pin. Leave floating. |
| PGND1 | 8 | G | Power ground to low-side MOSFET. Connect to system ground. Connect a high-quality bypass capacitor or capacitors between this pin and VIN1. |
| VIN1 | 9 | P | Input supply to the regulator. Connect high-quality bypass capacitors from this pin to PGND1. Provide a low-impedance connection to VIN2. |
| SW | 10 | P | Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI. |
| VIN2 | 11 | P | Input supply to the regulator. Connect high-quality bypass capacitors from this pin to PGND2. Provide a low-impedance connection to VIN1. |
| PGND2 | 12 | G | Power ground to internal low-side MOSFET. Connect to system ground. Connect high-quality bypass capacitors between this pin and VIN2. |
| BIAS | 13 | P | Input to internal voltage regulator. If configured for fixed VOUT, connect this pin to the VOUT node to close the control loop. If configured for an adjustable VOUT, connect this pin to the VOUT node or an external bias supply from 3.3V to 30V. If no external supply is used, tie the pin to GND. |
| VCC | 14 | P | Internal LDO output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Can be used for logic pull-up to control or flag pins. A 2.2μF capacitor internally connects from VCC to AGND. |
| NC | 15 | — | No connect pin. Leave floating. |
| PG | 16 | O | Power Good flag output. Open drain output that goes low if VOUT is outside of the specified regulation window. |
| GND | 17, 18 | G | Exposed ground pad. Connect to system GND on the PCB. This pin is a major heat dissipation path for the die. The pad must be used for heat sinking by soldering to the GND copper on a PCB. Implementing as many thermal vias as suggested in the example board layout makes sure of the lowest package thermal resistance and best possible thermal performance. |
| BOOT | 19 | P | Bootstrap pin for internal high-side driver circuitry. A 100nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. |