The control loop of the TPS7H4012 is described in Section 9.3.9. The component selection for compensating this device is as shown below. Other industry standard approaches for compensating a peak current mode control buck regulator are also acceptable.

Figure 10-2 Type II Compensation With Simplified Loop

1. Determine the desired crossover frequency, f_CO(desired). A good starting rule of thumb is to set the crossover frequency to one-tenth of the switching frequency. This generally provides a good transient response and maintain that the modulator poles do not degrade the phase margin. For this design, a more conservative crossover frequency target of 33kHz is selected.

2. Determine the required gain from the compensated error amplifier using Equation 22:
   Equation 22. $A_{VM}=\frac{2\pi \times f_{CO\left(desired\right)}\times C_{OUT}}{g_{mps}}$

   Where g_mps is the power stage transconductance for the selected current limit. For this design with f_CO(desired) = 33kHz, C_OUT = 693.1μF, g_mps = 11.2S, a value for A_VM of 12.8V/V is obtained.

3. R_COMP can be determined by Equation 23:
   Equation 23. $R_{COMP}=\frac{A_{VM}}{g_{mEA}}\times \frac{VOUT}{V_{REF}}$

   where gm_EA is the transconductance of the error amplifier (1650μS typ) and V_REF is the reference voltage (0.6V typ). A value of 42.77kΩ is calculated and a nearby standard resistor of 42.7kΩ was selected.

4. Calculate the power stage dominate pole determined by Equation 24:
   Equation 24. $f_{P,PS}=\frac{I_{OUT}}{2\pi \times C_{OUT}\times VOUT}$

   For this design, the dominate pole is calculated to be at 0.42kHz.

5. Place a compensation zero at the dominant pole by selecting C_COMP as determined by Equation 25:
   Equation 25. $C_{COMP}=\frac{1}{2\pi \times f_{P,PS}\times R_{COMP}}$

   For this design, C_COMP is calculated to be 8.93nF and a nearby standard capacitor value of 8.2nF was selected.

6. Calculate the ESR zero from the output capacitor bank by Equation 24:
   Equation 26. $f_{1,ESR}=\frac{1}{2\pi \times ESR\times C_{OUT}}$

   For this design, the ESR zero is calculated to be at 93.73kHz.

7. C_HF is used to cancel the zero from the equivalent series resistance (ESR) of the output capacitor C_OUT. It is calculated using Equation 27:
   Equation 27. $C_{HF}=\frac{1}{R_{COMP}\times 2\pi \times f_{Z,ESR}}$

   Note that if the ESR zero is higher than half the switching frequency, use half the switching frequency instead of the ESR zero in Equation 27. For this design, C_HF is calculated to be 39.77pF and a nearby standard capacitor value of 22pF is selected.