SNVSD08A February 2026 – October 2026 LM34938-Q1
PRODUCTION DATA
Table 9-1 lists the memory-mapped registers for the LM34938-Q1 registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 0x3 | CLEAR_FAULTS | CLEAR_FAULTS | Section 9.1 |
| 0xC | VOUT_TARGET1_LSB | VOUT_TARGET1_LSB | Section 9.2 |
| 0xD | VOUT_TARGET1_MSB | VOUT_TARGET1_MSB | Section 9.3 |
| 0x21 | USB_PD_STATUS_0 | USB_PD_STATUS_0 | Section 9.4 |
| 0x78 | STATUS_BYTE | STATUS_BYTE | Section 9.5 |
| 0x81 | USB_PD_CONTROL_0 | USB_PD_CONTROL_0 | Section 9.6 |
| 0xD0 | MFR_SPECIFIC_D0 | MFR_SPECIFIC_D0 | Section 9.7 |
| 0xD1 | MFR_SPECIFIC_D1 | MFR_SPECIFIC_D1 | Section 9.8 |
| 0xD2 | MFR_SPECIFIC_D2 | MFR_SPECIFIC_D2 | Section 9.9 |
| 0xD3 | MFR_SPECIFIC_D3 | MFR_SPECIFIC_D3 | Section 9.10 |
| 0xD4 | MFR_SPECIFIC_D4 | MFR_SPECIFIC_D4 | Section 9.11 |
| 0xD6 | MFR_SPECIFIC_D6 | MFR_SPECIFIC_D6 | Section 9.12 |
| 0xD7 | MFR_SPECIFIC_D7 | MFR_SPECIFIC_D7 | Section 9.13 |
| 0xD8 | MFR_SPECIFIC_D8 | MFR_SPECIFIC_D8 | Section 9.14 |
| 0xDA | IVP_VOLTAGE | IVP_VOLTAGE | Section 9.15 |
Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CLEAR_FAULTS is shown in Table 9-3.
Return to the Summary Table.
clear all latched status flags
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CLEAR_FAULTS | R | b | accessing the address is enough to clear fault |
VOUT_TARGET1_LSB is shown in Table 9-4.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | VOUT_A | R/W | 11111010b | Output target Voltage Logical Register Vout Setting Lower Limit: 0V Upper Limit: 48 V Step size: 20 mV or 10 mV depending on SEL__FB_DIV20 Value Calculation for 20mV Equation 3 Value Calculation for 10mV Equation 2 |
VOUT_TARGET1_MSB is shown in Table 9-5.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 3-0 | VOUT_A | R/W | b | Output target Voltage Logical Register Vout Setting Lower Limit: 0V Upper Limit: 48 V Step size: 20 mV or 10 mV depending on SEL__FB_DIV20 Value Calculation for 20mV Equation 3 Value Calculation for 10mV Equation 2 |
USB_PD_STATUS_0 is shown in Table 9-6.
Return to the Summary Table.
USB-PD STATUS REGISTER
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 6 | CC_OPERATION | R | b | Instantaneous status for constant current (CC) ILIM operation |
| 5-0 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
STATUS_BYTE is shown in Table 9-7.
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FAULT STATUS LOW BYTE
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUSY | R | b | unit is busy
|
| 6 | OFF | R | b | device not providing VOUT and/or unit is off
|
| 5 | VOUT | R | b | VOUT_OV fault
|
| 4 | IOUT | R | b | IOUT_OC fault
|
| 3 | INPUT | R | b | VIN_UV fault
|
| 2 | TEMPERATURE | R | b | Temperature fault or warning
|
| 1 | CML | R | b | Comm, Logic, Memory event
|
| 0 | OTHER | R | b | other fault or warning
|
USB_PD_CONTROL_0 is shown in Table 9-8.
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USB-PD CONTROL REGISTER
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 1 | FORCE_DISCH | R/W | b | Activates Vo discharge
|
| 0 | CONV_EN2 | R/W | b | Enables the power stage
|
MFR_SPECIFIC_D0 is shown in Table 9-9.
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CONFIG_0 Device Configuration Register 0
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 6 | EN_NEG_CL_LIMIT | R/W | b | Enables ILIM for negative current limit, If disabled ILIM clamps pos I_L
|
| 5 | EN_VCC1 | R/W | 1b | Enables the VCC1 auxiliary LDO
|
| 4 | IMON_LIMITER_EN | R/W | b | Enables the Imon in limiter configuration
|
| 3 | HICCUP_EN | R/W | b | Enables Hiccup short circuit
|
| 2 | DRSS_EN | R/W | b | Enables Dual Spread Spectrum
|
| 1 | USLEEP_EN | R/W | b | Enables micro sleep mode
|
| 0 | CONV_EN | R/W | b | Enables the power stage
|
MFR_SPECIFIC_D1 is shown in Table 9-10.
Return to the Summary Table.
CONFIG_1 Device Configuration Register 1
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | EN_THER_WARN | R/W | b | Enables Thermal Warning
|
| 6-5 | THW_THRESHOLD | R/W | b | Selects the Thermal Warning Threshold
|
| 4 | EN_NINT | R/W | b | Configures the nFLT pin handler to act as interrupt pin or nFLT pin
|
| 3 | EN_DTRK_STARTOVER | R/W | 1b | Enables a direct start-up if DTRK is enabled without waiting for the DTRK PWM signal
|
| 2 | FORCE_BIASPIN | R/W | b | Enables the priority to supply VCC2 from BIAS by lowering the threshold.
|
| 1 | EN_BB_2P_FPWM | R/W | b | Enables 2phase BB switching in fPWM mode
|
| 0 | EN_BB_2P_PSM | R/W | 1b | Enables 2phase BB switching in PSM mode
|
MFR_SPECIFIC_D2 is shown in Table 9-11.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 6 | EN_ACTIVE_DVS | R/W | 1b | Enables the active down ramp for DVS using the discharge
|
| 5-4 | DVS_SLEW_RAMP | R/W | b | Sets the positive and negative Vo slew rate for DVS
|
| 3-2 | DISCHARGE_STRENGTH | R/W | b | Sets the discharge current for the Vo discharge
|
| 1 | DISCHARGE_CONFIG0 | R/W | 1b | Selects the discharge together with CONV_EN
|
| 0 | DISCHARGE_CONFIG1 | R/W | b | Selects the discharge until the VTH DISCH
|
MFR_SPECIFIC_D3 is shown in Table 9-12.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | EN_IVP | R/W | 1b | Enabled input voltage protection.
|
| 6 | SEL_IVR | R/W | b | Selected input voltage regulation instead of the input voltage protection.
|
| 5 | VDET_EN | R/W | 1b | Enables internal VDET function
|
| 4-0 | VDET_FALL | R/W | b | VDET falling threshold
|
MFR_SPECIFIC_D4 is shown in Table 9-13.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 4-0 | VDET_RISE | R/W | 11b | VDET rising threshold
|
MFR_SPECIFIC_D6 is shown in Table 9-14.
Return to the Summary Table.
PS_Config0 Power stage Configuration
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | CONFIG_SYNC_PIN | R/W | b | Selects the SYNC function to maintain parallel operation
|
| 5 | EN_CONST_TDEAD | R/W | b | Forces a constant deadtime for the setting of SEL_MIN_DEADTIME_GDRV. Disables frequency dependency of min Tdead
|
| 4 | SEL_SCALE_DT | R/W | 1b | Scales the gate driver dead time freq dependence and 2 MHz setpoint
|
| 3-2 | SEL_MIN_DEADTIME_GDRV | R/W | 1b | Defines the minimum dead time at fsw = 2Mhz for the gate driver
|
| 1-0 | BB_MIN_TIME_OFFSET | R/W | 1b | Scales the BB min Ton or Toff time for the gate refresh
|
MFR_SPECIFIC_D7 is shown in Table 9-15.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | NIL | R | b | This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned. |
| 5-4 | SEL_INDUC_DERATE | R/W | 1b | Select the inductor de-rating for PSM mode to slope
|
| 3-0 | SEL_SLOPE_COMP | R/W | 101b | Select slope comp current, as ratio of RT current
|
MFR_SPECIFIC_D8 is shown in Table 9-16.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SEL_FB_DIV20 | R/W | 1b | Select internal FB divider ratio of 20
|
| 6 | EN_CDC | R/W | b | Enables the cable drop compensation
|
| 5-4 | CDC_GAIN | R/W | b | Selects the Gain for the CDC voltage (1V) with respect to Vout
|
| 3-2 | SEL_DRV1_SEQ | R/W | 10b | Select the sequencing for the DRV 1 operation
|
| 1-0 | SEL_DRV1_SUP | R/W | 11b | Select the driver configuration for DRV1 pin
|
IVP_VOLTAGE is shown in Table 9-17.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | V_IVP | R/W | 11111111b | Input Overvoltage Protection and Regulation Threshold
|