SNVU770 June   2021 LM5157 , LM5157-Q1 , LM51571-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Electrical Parameters
  4. 3Application Schematic
  5. 4EVM Picture
  6. 5Test Setup and Procedure
    1. 5.1 EVM Test Setup Schematic
    2. 5.2 Test Equipment
  7. 6Test Data and Performance Curves
    1. 6.1 Efficiency
    2. 6.2 Output Regulation and Cross-Regulations
    3. 6.3 Steady-State Waveforms
    4. 6.4 Start-Up Waveforms
    5. 6.5 Dynamic Responses
    6. 6.6 Short-Circuit Protection
    7. 6.7 Bode Plots
    8. 6.8 Thermal Image
  8. 7Schematic
  9. 8Bill of Materials
  10. 9EVM Layout

Output Regulation and Cross-Regulations

GUID-20210416-CA0I-TXFT-CPZN-H4RNR4QTV5LH-low.svgFigure 6-2 Main Output Voltage Regulation vs Main Output Load (Io2, Io3, Io4 = 100%)
GUID-20210416-CA0I-CNGZ-C6FN-HRSNMWWZSHGL-low.svgFigure 6-4 Main Output Voltage Regulation vs Input Voltage (Io2, Io3, Io4 = 100%)
GUID-20210416-CA0I-CSFX-FLF5-GD1MHHJXRZWL-low.svgFigure 6-6 Voltage Regulation of Isolated Outputs vs Input Voltage at 50% load
GUID-20210416-CA0I-5G28-JCSQ-BGRZMD3JRPWB-low.svgFigure 6-3 Cross Regulation of Isolated Outputs vs Main Output Load (Io2, Io3, Io4 = 10%)
GUID-20210416-CA0I-VRQB-40ZR-PX3H5QTWFSBX-low.svgFigure 6-5 Voltage Regulation of Isolated Outputs vs Input Voltage at 10% load
GUID-20210416-CA0I-SHMN-Z5N1-CPPLZJTMFD3F-low.svgFigure 6-7 Voltage Regulation of Isolated Outputs vs Input Voltage at 100% load