SNVU857 November   2023 LMR66430-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Test Points
      2. 2.1.2 Jumpers
    2. 2.2 Operation
      1. 2.2.1 Quick Start
  8. 3Implementation Results
    1. 3.1 Test Results
      1. 3.1.1 LMR66430-2EVM Test Results
        1. 3.1.1.1 Noise and Thermal Performance
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  10. 5Additional Information
    1.     Trademarks

2.1.2 Jumpers

  • J1 — Connect J1:1-2 to enable the device or J1:2-3 to disable the device. To evaluate a unique EN_UVLO, please utilize the equations provided in the data sheet for calculating R5, then populate on the EVM, and remove the J1 jumper.
  • J2— Connect J2:1-2 to put the device in Auto mode or J2:2-3 for FPWM (fixed frequency). If synchronization to an external clock source is required, remove J2 jumper and hook-up clock to test point "SYNC."
  • J3 — PG is an open-drain, output signifying VOUT regulation. Connect J3:1-2 for VCC (3V) pull-up voltage, or, J3:2-3 for VOUT pull-up voltage. Note, the max voltage PG can sustain is 20 V.
GUID-20231026-SS0I-N81Q-CRSS-RLCHDX8VD8BD-low.svg Figure 2-2 Jumper Locations