SPRAD41 May   2022 AM623 , AM625

 

  1.   Trademarks
  2. 1Introduction
  3. 2AM62x Power Management Features
    1. 2.1 Low Power Modes
    2. 2.2 Active Power Management
    3. 2.3 Power Supply Simplification
    4. 2.4 Power Solutions
  4. 3Low Power Processor Architecture Considerations
  5. 4AM62x Power Consumption
  6. 5Power Estimation Tool
  7. 6Conclusion

2.1 Low Power Modes

The AM62x processor supports optimized low power modes with varying levels of power dissipation: Partial I/O mode to Deepsleep mode to Standby mode (sub mW to a few mW). Table 2-2 shows a high-level description of various low-power modes supported on AM62x processors.

Table 2-2 AM62x Low Power Modes
Low Power Modes Wakeup Sources Application State and Use Case
Partial I/O CANUART I/O Bank pins The entire SoC is OFF except I/O pins in CANUART I/O bank to maintain I/O wakeup capability from CANUART I/O Bank I/O pins.
DeepSleep GP Timers, RTC Timer, UART, I2C, MCU GPIO0, I/O Daisy Chain, USB wakeup events Core domain register information will be lost. On-chip peripheral register (context) information of core domain needs to be saved by application to DDR before entering this mode. DDR is in self-refresh. Boot ROM executes and branches to peripheral context restore for wakeup, followed by system resume. This mode is primarily used for Suspend to RAM for battery lifetime or backup operation.
MCU Only DeepSleep wakeup events, Interrupt evens supported in MCU channel The MCU subsystem runs at the MCU PLL clock. The rest of the SoC status is the same as DeepSleep. DDR is in self-refresh. MCU can run applications with MCU domain peripherals while in this low power mode.
Standby Any SoC interrupt event On-chip contents are fully preserved. Any SoC interrupt event can cause a wakeup event from this low power mode. A53 and MCU M4F are in WFI or power down. DDR memory is in self-refresh. The device can run low-level processing with non-Wakeup/MCU domain peripherals and support wakeup from thos peripherals.

Partial I/O: I/O pins and small logic in the CANUART I/O Bank are active, and the rest of the SoC is turned off. The user can use the I/O pins to aggregate multiple I/O wakeup events and toggle the PMIC_LPM_EN pin to enable PMIC or discrete power solution when an I/O wakeup event is triggered. The information on the I/O wakeup event is logged in the MMR in the CANUART I/O bank and helps the software to distinguish between cold boot and wakeup to respond to the wakeup event faster. This mode can be used to support CAN wakeup or Ethernet Wakeup.

DeepSleep: DeepSleep mode enables lower power consumption than Standby or MCU-Only. DeepSleep mode is typically used during inactivity when the user requires very low power while waiting for an event that requires processing or higher performance. DeepSleep is the lowest power mode which still includes DDR in self-refresh, so wakeup events do not require a full cold boot, significantly reducing wakeup latencies. The lowest power in this mode can be achieved by disabling both oscillators when the RTC or other timer function is not required.

MCU Only: MCU-Only can be used for low power use cases that require low-level processing during a low power mode. The status of the SoC is the same as DeepSleep, except the MCU channel is fully active to run applications with MCU channel resources and peripherals. Any interrupt event in the MCU channel can initiate a wakeup from MCU-Only, and the wakeup events supported in DeepSleep can also trigger wakeup from MCU-Only.

Standby:The device can be placed in Standby mode to reduce power consumption during low activity levels. This first level of power management allows you to maintain the device context for fast resume times. Standby state results in lower power consumption than Active mode but require the user to save the switched-off power domain context to On-Chip Memory or DDR and restore the contexts to resume properly upon wakeup.