3 Low Power Processor Architecture Considerations

Hardware and software co-design is extremely critical to power and latency optimization. Figuring out the right hardware-software boundary, identifying which function is in hardware and which function is in software earlier on during the definition is key. Simplifying software sequences for low power mode entry and exit modes by eliminating save and restore of configuration settings supported by innovative new features such as USB and DDR Reset Isolation and Retention schemes. Optimizing IO states (pull-ups and pull-downs) based on low power use-case and ability to put IOs in retention enhances the system robustness and reliability.

Early in the development phase, several different HW/SW partitions were evaluated, to determine best implementation to meet overall system use-cases and goals (cost, performance, power, and latency). The AM62x processor is mainly divided into 4 domains, as shown in Figure 3-1.

Application domain comprising of high-performance CPUs, HW accelerators, and high-speed peripherals. This domain is further divided into various sub-systems with internal power switches. Depending on the system use-cases, these sub-systems can be completely powered-down using the internal power-domain switches. For example: un-used CPU cores in a cluster, HW accelerators (graphics, display), and so forth. In addition, during DeepSleep and MCU only low power modes, application domain is put to lowest power mode through internal subsystem power gating.

MCU domain comprising of real-time CPUs and peripherals. This domain can be configured to operate completely independent from the application domain: a key differentiating feature in several automotive, industrial, and battery-operated applications. During DeepSleep mode, the MCU domain can be powered-down through internal power switches.

Wake-up domain comprising of Power Management CPU and system components such as clocks, resets, power, and wake-up. This domain is responsible for device boot-up, resource configuration and management, and low power management. Hardware isolation is built around this domain to ensure that clear separation between application and MCU domains. By carefully partitioning the responsibilities between hardware and software functions, Sitara MPU devices achieve simpler and robust low power mode entry and exit sequences. In addition, to improve low power mode entry/exit latencies, Sitara MPU devices developed innovative new features such as USB and DDR reset isolation and retention schemes to avoid complex software sequences that require peripheral configuration save and restore.