SPRAD89 March   2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Use-case Considerations
  5. 3Interfacing the High Voltage Sensor
    1. 3.1 Consideration for Proper ADC Sampling
    2. 3.2 Handling High Impedance Sensor
  6. 4Performance Considerations
    1. 4.1 ADC Gain, Offset, INL & DNL
    2. 4.2 SNR Consideration
    3. 4.3 Performance Advantage
  7. 5Conclusion
  8. 6References

4.2 SNR Consideration

For a 12b ADC, 5 V to 3.3 V SNR degradation will cause about ½ LSB SNR loss, which is usually not very significant. The ideal 12 Bit ADC SNR will degrade from 74 dB to 70.6 dB with a 5 V to 3.3 V attenuation The below definitions and equations explain the degradation.

Source noise: Any noise embedded in signal Vin, will also get attenuated with the resistor divider circuit, hence it will not affect overall Signal to Noise Ratio (SNR) performance.

Common ground noise: The common ground noise will not be attenuated by the resistor divider circuit, hence that will have an impact on the SNR. The SNR will be degraded by the attenuation factor. For a 5 V to 3.3 V signal attenuation, the SNR degradation will be:

Equation 9. 3.3 / 5   =   0.66  
Equation 10. 20   l o g   ( 0.66 )   ≅   - 3.6   d B

An N bit ADC’s ideal SNR is equal to

Equation 11. I d e a l   S N R   =   6.02   ×   N   +   1.76   d B