SPRADP5A January   2026  – September 2026 AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stackup
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stackup
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References
  10. 7Revision History

3.5.1 Simulation Setup

Setup the IBIS simulation with the following steps:

  1. Extract S-parameter files for eMMC signals on the board.
    1. It is okay to use 2.5D extractor for board signals.
  2. Obtain the SoC IBIS model at TI.com under the AM62Px product page.
  3. Obtain the S-parameter model for the SoC package from your TI representative (provided separately under NDA).
    1. It is required to use the S-parameter SoC package model as the pass/fail checks documented in Section 3.5.5 are derived assuming a system with the S-parameter SoC package model.
    2. Simulations that use the SoC IBIS RLC package model instead of the S-parameter SoC package model produce optimistic results and applicable margin calculations are not available.
    3. The SoC IBIS RLC package model must not be used. Verify the SoC IBIS model does not have a check mark next to Package Parasitics in the simulation setup.
  4. Obtain the eMMC device IBIS model from the eMMC vendor.
    1. This IBIS model must include package RLC model for the eMMC device.
  5. Build up the simulation netlist as shown in a simulator of your choice.
    1. Set up the system-level schematic in the simulator by connecting the SoC IBIS model, board model, power supplies, and eMMC device IBIS model.
    2. A typical system-level eMMC schematic is shown in Figure 3-2.
  6. Build up the process, voltage, temperature corners you are going to simulate.
    1. Recommended to simulate across all processes, voltages, temperatures supported by the IBIS model
      • Typical (TT):
        • IO Voltage = 1.8V
        • Temperature = 30C
      • Minimal (SS):
        • IO Voltage = 1.8V × 0.9 = 1.62V
        • Temperature = 125C
      • Maximal (FF):
        • IO Voltage = 1.8V × 1.1 = 1.98V
        • Temperature = -40C
    2. The nominal drive strength specified by JEDEC is 50Ω. However, the customer can try other drive strengths if they are found to yield better signal integrity margins in their simulations.
  7. Review Section 3.5.3 and ensure these best practices are being followed prior to running simulations.
  8. Use all attack patterns provided in Section 3.5.2 as stimulus for simulations.
  9. Analyze the results in a waveform analysis tool and use the pass/fail checks from Section 3.5.5 to assess the quality of results
Important: Do not set up a power-aware simulation. Power supply noise is controlled through Loop Inductance and AC Impedance checks as outlined in previous sections of this document.
Typical System-Level eMMC Schematic Figure 3-2 Typical System-Level eMMC Schematic