SPRADR2 June   2025 AM2431 , AM2432 , AM2434 , AM623 , AM625 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Tools for Arm®-based Processors
    1. 2.1 Code Composer Studio™ (CCS)
    2. 2.2 DCC ISP Tuning
    3. 2.3 DDR Margin Analysis
    4. 2.4 K3conf
    5. 2.5 OTP Keywriter
    6. 2.6 Power Estimation (PET)
    7. 2.7 Snagfactory Flashing
    8. 2.8 SysConfig
      1. 2.8.1 Clock Tree
      2. 2.8.2 DDR Config
      3. 2.8.3 Memory Configurator
      4. 2.8.4 Pinmux
      5. 2.8.5 Resource Partitioning
      6. 2.8.6 Software Configuration
    9. 2.9 UniFlash
  6. 3Summary Table
  7. 4References

2.8.2 DDR Config

The DDR Config is intended to simplify the process of configuring the DDR Subsystem Controller and PHY to interface to DDR4 and LPDDR4 memory devices. The tools consists of a number of parameters to be input by the user (based on the memory device data sheet, board design, and topology), and outputs a file to be used by software to properly initialize and train the selected memory.