SPRSP79D February   2023  – August 2026 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
          1.        22
          2.        23
          3.        24
          4.        25
      4. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
          1.        28
        2. 5.3.3.2 WKUP Domain
          1.        30
      5. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
          1.        33
          2.        34
          3.        35
          4.        36
          5.        37
          6.        38
          7.        39
        2. 5.3.4.2 MCU Domain
          1.        41
          2.        42
        3. 5.3.4.3 WKUP Domain
          1.        44
      6. 5.3.5  I3C
        1. 5.3.5.1 MCU Domain
          1.        47
      7. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
          1.        50
          2.        51
          3.        52
          4.        53
          5.        54
          6.        55
          7.        56
          8.        57
          9.        58
          10.        59
          11.        60
          12.        61
          13.        62
          14.        63
          15.        64
          16.        65
          17.        66
          18.        67
        2. 5.3.6.2 MCU Domain
          1.        69
          2.        70
      8. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
          1.        73
          2.        74
          3.        75
          4.        76
          5.        77
          6.        78
          7.        79
        2. 5.3.7.2 MCU Domain
          1.        81
          2.        82
      9. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
          1.        85
          2.        86
          3.        87
          4.        88
          5.        89
          6.        90
          7.        91
          8.        92
          9.        93
          10.        94
        2. 5.3.8.2 MCU Domain
          1.        96
        3. 5.3.8.3 WKUP Domain
          1.        98
      10. 5.3.9  MDIO
        1. 5.3.9.1 MAIN Domain
          1.        101
          2.        102
        2. 5.3.9.2 MCU Domain
          1.        104
      11. 5.3.10 UFS
        1. 5.3.10.1 MAIN Domain
          1.        107
      12. 5.3.11 CPSW2G
        1. 5.3.11.1 MAIN Domain
          1.        110
        2. 5.3.11.2 MCU Domain
          1.        112
      13. 5.3.12 SGMII
        1. 5.3.12.1 MAIN Domain
          1.        115
      14. 5.3.13 ECAP
        1. 5.3.13.1 MAIN Domain
          1.        118
          2.        119
          3.        120
      15. 5.3.14 EQEP
        1. 5.3.14.1 MAIN Domain
          1.        123
          2.        124
          3.        125
      16. 5.3.15 EPWM
        1. 5.3.15.1 MAIN Domain
          1.        128
          2.        129
          3.        130
          4.        131
          5.        132
          6.        133
          7.        134
      17. 5.3.16 USB
        1. 5.3.16.1 MAIN Domain
          1.        137
      18. 5.3.17 Display Port
        1. 5.3.17.1 MAIN Domain
          1.        140
      19. 5.3.18 PCIE
        1. 5.3.18.1 MAIN Domain
          1.        143
      20. 5.3.19 SERDES
        1. 5.3.19.1 MAIN Domain
          1.        146
          2.        147
          3.        148
          4.        149
      21. 5.3.20 DSI
        1. 5.3.20.1 MAIN Domain
          1.        152
          2.        153
      22. 5.3.21 CSI
        1. 5.3.21.1 MAIN Domain
          1.        156
          2.        157
          3.        158
      23. 5.3.22 MCASP
        1. 5.3.22.1 MAIN Domain
          1.        161
          2.        162
          3.        163
          4.        164
          5.        165
      24. 5.3.23 DMTIMER
        1. 5.3.23.1 MAIN Domain
          1.        168
        2. 5.3.23.2 MCU Domain
          1.        170
      25. 5.3.24 CPTS
        1. 5.3.24.1 MAIN Domain
          1.        173
        2. 5.3.24.2 MCU Domain
          1.        175
      26. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
          1.        178
      27. 5.3.26 GPMC
        1. 5.3.26.1 MAIN Domain
          1.        181
      28. 5.3.27 MMC
        1. 5.3.27.1 MAIN Domain
          1.        184
          2.        185
      29. 5.3.28 OSPI
        1. 5.3.28.1 MCU Domain
          1.        188
          2.        189
      30. 5.3.29 Hyperbus
        1. 5.3.29.1 MCU Domain
          1.        192
      31. 5.3.30 Emulation and Debug
        1. 5.3.30.1 MAIN Domain
          1.        195
          2.        196
      32. 5.3.31 System and Miscellaneous
        1. 5.3.31.1 Boot Mode configuration
          1.        199
        2. 5.3.31.2 Clock
          1.        201
          2.        202
        3. 5.3.31.3 System
          1.        204
          2.        205
        4. 5.3.31.4 EFUSE
          1.        207
        5. 5.3.31.5 VMON
          1.        209
      33. 5.3.32 Power
        1.       211
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On-Hour (POH) Limits
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  LVCMOS Electrical Characteristics
      9. 6.6.9  USB2PHY Electrical Characteristics
      10. 6.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 6.6.11 UFS M-PHY Electrical Characteristics
      12. 6.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 6.6.13 DDR0 Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALY Package
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1  Power Supply Slew Rate Requirement
        2. 6.10.2.2  Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3  Combined MCU and Main Domains Power- Down Sequencing - Option 1
        4. 6.10.2.4  Combined MCU and Main Domains Power- Down Sequencing - Option 2
        5. 6.10.2.5  Isolated MCU and Main Domains Power- Up Sequencing
        6. 6.10.2.6  Isolated MCU and Main Domains Power- Down Sequencing - Option 1
        7. 6.10.2.7  Isolated MCU and Main Domains Power- Down Sequencing - Option 2
        8. 6.10.2.8  Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        9. 6.10.2.9  Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        10. 6.10.2.10 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input and Output Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Module and Peripheral Clocks Frequencies
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.10.5.2.2 CPSW2G RMII Timings
            1. 6.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.10.5.2.3 CPSW2G RGMII Timings
            1. 6.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 6.10.5.3  CSI-2
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  DSS
        6. 6.10.5.6  eCAP
          1. 6.10.5.6.1 Timing Requirements for eCAP
          2. 6.10.5.6.2 Switching Characteristics for eCAP
        7. 6.10.5.7  EPWM
          1. 6.10.5.7.1 Timing Requirements for eHRPWM
          2. 6.10.5.7.2 Switching Characteristics for eHRPWM
        8. 6.10.5.8  eQEP
          1. 6.10.5.8.1 Timing Requirements for eQEP
          2. 6.10.5.8.2 Switching Characteristics for eQEP
        9. 6.10.5.9  GPIO
          1. 6.10.5.9.1 GPIO Timing Requirements
          2. 6.10.5.9.2 GPIO Switching Characteristics
        10. 6.10.5.10 GPMC
          1. 6.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.10.5.10.4 GPMC0 IOSET
        11. 6.10.5.11 HyperBus
          1. 6.10.5.11.1 Timing Requirements for HyperBus
          2. 6.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.10.5.12 I2C
        13. 6.10.5.13 I3C
        14. 6.10.5.14 MCAN
        15. 6.10.5.15 MCASP
        16. 6.10.5.16 MCSPI
          1. 6.10.5.16.1 MCSPI — Controller Mode
          2. 6.10.5.16.2 MCSPI — Peripheral Mode
        17. 6.10.5.17 MMCSD
          1. 6.10.5.17.1 MMC0 - eMMC Interface
            1. 6.10.5.17.1.1 Legacy SDR Mode
            2. 6.10.5.17.1.2 High Speed SDR Mode
            3. 6.10.5.17.1.3 High Speed DDR Mode
            4. 6.10.5.17.1.4 HS200 Mode
            5. 6.10.5.17.1.5 HS400 Mode
          2. 6.10.5.17.2 MMC1 - SD/SDIO Interface
            1. 6.10.5.17.2.1 Default Speed Mode
            2. 6.10.5.17.2.2 High Speed Mode
            3. 6.10.5.17.2.3 UHS–I SDR12 Mode
            4. 6.10.5.17.2.4 UHS–I SDR25 Mode
            5. 6.10.5.17.2.5 UHS–I SDR50 Mode
            6. 6.10.5.17.2.6 UHS–I DDR50 Mode
            7. 6.10.5.17.2.7 UHS–I SDR104 Mode
        18. 6.10.5.18 CPTS
          1. 6.10.5.18.1 CPTS Timing Requirements
          2. 6.10.5.18.2 CPTS Switching Characteristics
        19. 6.10.5.19 OSPI
          1. 6.10.5.19.1 OSPI0/1 PHY Mode
            1. 6.10.5.19.1.1 OSPI0/1 With PHY Data Training
            2. 6.10.5.19.1.2 OSPI Without Data Training
              1. 6.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.10.5.19.1.2.4 OSPI Switching Characteristics – PHY DDR Mode
          2. 6.10.5.19.2 OSPI0/1 Tap Mode
            1. 6.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.10.5.20 OLDI
          1. 6.10.5.20.1 OLDI Switching Characteristics
        21. 6.10.5.21 PCIE
        22. 6.10.5.22 Timers
          1. 6.10.5.22.1 Timing Requirements for Timers
          2. 6.10.5.22.2 Switching Characteristics for Timers
        23. 6.10.5.23 UART
          1. 6.10.5.23.1 Timing Requirements for UART
          2. 6.10.5.23.2 UART Switching Characteristics
        24. 6.10.5.24 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 JTAG Timing Requirements
            2. 6.10.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 VPAC
      3. 7.3.3 DMPAC
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG and EMU
      4. 8.1.4 Reset
      5. 8.1.5 Unused Pins
      6. 8.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal Flash devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

4 Device Comparison

Table 4-1 shows the features of the SoC.

Note: Availability of features listed in this Device Comparison table are a function of shared IO pins, where IO signals associated with many of the features are multiplexed to a limited number of pins. Use the SysConfig tool to assign signal functions to pins. This tool provides a better understanding of limitations associated with pin multiplexing.
Note: To understand what device features are currently supported by TI Software Development Kits (SDKs), see the TDA4VH Software Build Sheet (PROCESSOR-SDK-J784S4).
Table 4-1 Device Comparison
FEATURES(10) REFERENCE
NAME		 TDA4VH88 TDA4AH88 TDA4VP88 TDA4AP88
FEATURES
WKUP_CTRL_MMR_CFG0_JTAG_USER_ID[31:16]
DEVICE_ID register bit field value(9)(10)		 0x2BC0 0x2BC8 0x2BD0 0x2BD8
PROCESSORS AND ACCELERATORS
Speed Grades T T T T
Arm Cortex-A72 Microprocessor Subsystem Arm A72 Octal Core
Arm Cortex-R5F Arm R5F Octal Core
Lockstep Optional(1)
Security Management SMS Yes
Security Accelerators SA Yes
Floating Point, Vector C7™ DSP C7 DSP Quad Core Tri Core
Deep Learning Accelerator MMA Quad Core Tri Core
Graphics Accelerator IMG BXS-4-64 GPU Yes No Yes No
Depth and Motion Processing Accelerators DMPAC Yes
Vision Processing Accelerators VPAC 2
Video Encoder / Decoder VENC/ VDEC Enc/Dec 960 MP/s Enc/Dec 480 MP/s
SAFETY AND SECURITY
Safety Targeted Safety Optional(1)
Device Security Security Optional(2)
AEC-Q100 Qualified Q1 Optional(3)
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM 3x512KB SRAM
On-Chip Shared Memory (RAM) in MCU Domain MCU_MSRAM 1MB SRAM
Multicore Shared Memory Controller MSMC 8MB (On-Chip SRAM with ECC)
LPDDR4 DDR Subsystem DDRSS0(5) 32-b w/ inline ECC
DDRSS1(5) 32-b w/ inline ECC
DDRSS2(4)(5) 32-b w/ inline ECC
DDRSS3(4)(5) 32-b w/ inline ECC No
SECDED 7-Bit
General-Purpose Memory Controller GPMC Yes
PERIPHERALS
Display Subsystem DSS Yes
DSI 4L TX 2
eDP 4L 1
DPI 1
Modular Controller Area Network Interface with Full CAN-FD Support MCAN 20
General-Purpose I/O GPIO 155
Inter-Integrated Circuit Interface I2C 10
Improved Inter-Integrated Circuit Interface I3C 1
Analog-to-Digital Converter ADC 2
Capture Subsystem with Camera Serial Interface (CSI2) CSI2.0 4L RX 3
CSI2.0 4L TX 2
Multichannel Serial Peripheral Interface MCSPI 11
Multichannel Audio Serial Port MCASP0 16 Serializers
MCASP1 5 Serializers
MCASP2 5 Serializers
MCASP3 3 Serializers
MCASP4 5 Serializers
MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC
(8-bits)
MMCSD1 SD/SDIO
(4-bits)
Universal Flash Storage UFS 2L Yes
Flash Subsystem (FSS) OSPI0 8-bits(8)
OSPI1(11) 4-bits
HyperBus Yes(8)
4x PCI Express Port with Integrated PHY PCIE 2x4L or 4x2L(6) 1x4L or 2x2L(6)(12)
Ethernet Interfaces MCU CPSW2G RMII or RGMII
MAIN CPSW2G RMII or RGMII
CPSW9G 8 port SERDES(6) 4 port SERDES(6)(7)
General-Purpose Timers TIMER 30
Enhanced High Resolution Pulse-Width Modulator Module eHRPWM 6
Enhanced Capture Module eCAP 3
Enhanced Quadrature Encoder Pulse Module eQEP 3
Universal Asynchronous Receiver and Transmitter UART 12
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY USB0 Yes(6)
(1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the Device Type (Y) identifier in the Nomenclature Description table.
(2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Nomenclature Description table.
(3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Nomenclature Description table.
(4) DDRSS2 and DDRSS3 are not available on the 27mm package variant of this SoC. DDR2/DDR3 should be not be used if software compatibility is desired with systems that use the 27mm package
(5) DDRSS0, DDRSS1, DDRSS2 and DDRSS3 must always be used in incremental order. For instance, when using a single LPDDR component, it must be connected to DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_* and DDR1_* interfaces, and so forth.
(6) DP, SGMII, USB3.0, and PCIE share total of 16 SerDes lanes. SERDES2 is not available on the 27mm package variant of this SoC. SERDES2 should not be used if software compatibility is desired with systems that use the 27mm package.
(7) TDA4xH CPSW supports up to 8 ports using the following instances and signals and modes of operation:
  • PORT1 Signals: SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII
  • PORT2 Signals: SGMII2, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII
  • PORTn (n=3 thru 8) Signals: SGMIIn, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII
If QSGMII is used on any SGMII Port 1 thru 4, then SGMII1/2/3/4 cannot be used for Ethernet functionality since all 4 internal CPSW ports map to the selected QSGMII SERDES port.
If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW ports map to the selected QSGMII SERDES port.TDA4xP CPSW supports up to 4 ports. To maximize pin muxing flexibility, the system designer can choose based on any available PORTS, but must limit the total number of ports used to four or fewer.
(8) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.
(9) For more details about the WKUP_CTRL_MMR_CFG0_JTAG_USER_ID register and DEVICE_ID bit field, see the device TRM.
(10) XJ784S4 is the base part number for the superset device. Software should constrain the features used to match the intended production device. (WKUP_CTRL_MMR_CFG0_JTAG_USER_ID[31:16] "DEVICE_ID" register bit field value: 0x2B21.)
(11) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.
(12) TDA4xP PCIe supports 1x4L or 2x2L options. To maximize pin muxing flexibility, the system designer can choose any available PCIe instances or available PORTS, but must limit to a maximum of 1x4L or 2x2L.