SPRSPB0B December   2024  – April 2026 AM2752-Q1 , AM2754-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 ANJ Pin Diagram
    2. 5.2 Pin Attributes
      1.      12
      2.      13
    3. 5.3 Signal Descriptions
      1.      15
      2. 5.3.1  ADC
        1.       17
      3. 5.3.2  Audio Clock References
        1.       19
      4. 5.3.3  CPSW
        1.       21
        2.       22
        3.       23
        4.       24
        5.       25
      5. 5.3.4  CPTS
        1.       27
      6. 5.3.5  ECAP
        1.       29
        2.       30
        3.       31
        4.       32
        5.       33
        6.       34
      7. 5.3.6  Emulation and Debug
        1.       36
        2.       37
      8. 5.3.7  EPWM
        1.       39
        2.       40
        3.       41
        4.       42
      9. 5.3.8  GPIO
        1.       44
        2.       45
        3.       46
      10. 5.3.9  HYPERBUS
        1.       48
      11. 5.3.10 I2C
        1.       50
        2.       51
        3.       52
        4.       53
        5.       54
        6.       55
        7.       56
        8.       57
      12. 5.3.11 MCAN
        1.       59
        2.       60
        3.       61
        4.       62
        5.       63
      13. 5.3.12 MCASP
        1.       65
        2.       66
        3.       67
        4.       68
        5.       69
      14. 5.3.13 MLB
        1.       71
      15. 5.3.14 MMC
        1.       73
      16. 5.3.15 OSPI
        1.       75
        2.       76
      17. 5.3.16 Power Supply
        1.       78
      18. 5.3.17 Reserved and No Connect
        1.       80
      19. 5.3.18 System and Miscellaneous
        1.       82
        2.       83
        3.       84
        4.       85
      20. 5.3.19 SPI
        1.       87
        2.       88
        3.       89
        4.       90
        5.       91
      21. 5.3.20 TIMER
        1.       93
        2.       94
      22. 5.3.21 UART
        1.       96
        2.       97
        3.       98
        4.       99
        5.       100
        6.       101
        7.       102
        8.       103
      23. 5.3.22 USB
        1.       105
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) for AEC - Q100 devices
    3. 6.3  Electrostatic Discharge (ESD) for non AEC - Q100 devices
    4. 6.4  Power-On Hours (POH) Summary
    5. 6.5  Automotive Temperature Profile
    6. 6.6  Recommended Operating Conditions
    7. 6.7  Device Speed Grades
    8. 6.8  Power Consumption Summary
    9. 6.9  Electrical Characteristics
      1. 6.9.1 I2C Open-Drain and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.9.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.9.3 High-Frequency Oscillators (MCU_OSC0 and OSC1) Electrical Characteristics
      4. 6.9.4 Low-Frequency Oscillator (WKUP_LFOSC0) Electrical Characteristics
      5. 6.9.5 SDIO Electrical Characteristics
      6. 6.9.6 Analog-to-Digital Converter (ADC)
      7. 6.9.7 LVCMOS Electrical Characteristics
      8. 6.9.8 USB2PHY Electrical Characteristics
    10. 6.10 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.10.1 VPP Specifications
      2. 6.10.2 Hardware Requirements
      3. 6.10.3 Programming Sequence
      4. 6.10.4 Impact to Your Hardware Warranty
    11. 6.11 Thermal Resistance Characteristics
      1. 6.11.1 Package Thermal Characteristics
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Timing Parameters and Information
      2. 6.12.2 Power Supply Requirements
        1. 6.12.2.1 Power Supply Slew Rate Requirement
        2. 6.12.2.2 Power Supply Sequencing
          1. 6.12.2.2.1 Power-Up Sequencing without IO Retention
          2. 6.12.2.2.2 Power-Up Sequencing with IO Retention
          3. 6.12.2.2.3 Power-Up Sequencing - IO Retention Wakeup
          4. 6.12.2.2.4 Power-Down Sequencing
      3. 6.12.3 System Timing
        1. 6.12.3.1 Reset Timing
          1.        Reset Timing Conditions
          2.        MCU_PORz Timing Requirements
          3.        145
          4.        RESETSTATz Switching Characteristics
          5.        MCU_RESETz Timing Requirements
          6.        RESETSTATz Switching Characteristics
          7.        EMUx Timing Requirements
          8.        150
          9.        BOOTMODE Timing Requirements
        2. 6.12.3.2 Error Signal Timing
          1.        Error Signal Timing Conditions
          2.        MCU_ERRORn Switching Characteristics
          3.        155
        3. 6.12.3.3 Clock Timing
          1.        Clock Timing Conditions
          2.        Clock Timing Requirements
          3.        159
          4.        Clock Switching Characteristics
          5.        161
      4. 6.12.4 Clock Specifications
        1. 6.12.4.1 Input Clocks / Oscillators
          1. 6.12.4.1.1 MCU_OSC0 and OSC1 Internal Oscillator Clock Source
            1. 6.12.4.1.1.1 HFOSC (MCU_OSC0 and OSC1) Crystal Circuit Requirements
            2. 6.12.4.1.1.2 HFOSC (MCU_OSC0 and OSC1) Switching Characteristics - Crystal Mode
            3. 6.12.4.1.1.3 Load Capacitance
            4. 6.12.4.1.1.4 Shunt Capacitance
          2. 6.12.4.1.2 MCU_OSC0 and OSC1 LVCMOS Digital Clock Source
          3. 6.12.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
            1. 6.12.4.1.3.1 LFOSC (WKUP_LFOSC0) Crystal Circuit Requirements
            2. 6.12.4.1.3.2 LFOSC (WKUP_LFOSC0) Switching Characteristics - Crystal Mode
          4. 6.12.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.12.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.12.4.2 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.12.5 Peripherals
        1. 6.12.5.1  ATL
          1.        ATL Timing Conditions
          2.        ATL_AWS[x] Timing Requirements
          3.        ATL_BWS[x] Timing Requirements
          4.        ATL_PCLK Timing Requirements
          5.        ATCLK[x] Switching Characteristics
        2. 6.12.5.2  CPSW3G
          1. 6.12.5.2.1 CPSW3G MDIO Timing
            1.         CPSW3G MDIO Timing Conditions
            2.         CPSW3G MDIO Timing Requirements
            3.         CPSW3G MDIO Switching Characteristics
            4.         188
          2. 6.12.5.2.2 CPSW3G RMII Timing
            1.         CPSW3G RMII Timing Conditions
            2.         CPSW3G RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         192
            4.         CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         194
            6.         CPSW3G RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         196
          3. 6.12.5.2.3 CPSW3G RGMII Timing
            1.         CPSW3G RGMII Timing Conditions
            2.         CPSW3G RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3.         CPSW3G RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements - RGMII Mode
            4.         201
            5.         CPSW3G RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6.         CPSW3G RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         204
        3. 6.12.5.3  ECAP
          1.        ECAP Timing Conditions
          2.        ECAP Timing Requirements
          3.        208
          4.        ECAP Switching Characteristics
          5.        210
        4. 6.12.5.4  Emulation and Debug
          1. 6.12.5.4.1 Trace
            1.         Trace Timing Conditions
            2.         Trace Switching Characteristics
            3.         215
          2. 6.12.5.4.2 JTAG
            1.         JTAG Timing Conditions
            2.         JTAG Timing Requirements
            3.         JTAG Switching Characteristics
            4.         220
        5. 6.12.5.5  EPWM
          1.        EPWM Timing Conditions
          2.        EPWM Timing Requirements
          3.        224
          4.        EPWM Switching Characteristics
          5.        226
        6. 6.12.5.6  GPIO
          1.        GPIO Timing Conditions
          2.        GPIO Timing Requirements
          3.        GPIO Switching Characteristics
        7. 6.12.5.7  HyperBus
          1.        HyperBus Timing Conditions
          2.        HyperBus Timing Requirements
          3.        HyperBus 166MHz Switching Characteristics
          4.        HyperBus 100MHz Switching Characteristics
        8. 6.12.5.8  I2C
        9. 6.12.5.9  MCAN
          1.        MCAN Timing Conditions
          2.        MCAN Switching Characteristics
        10. 6.12.5.10 MCASP
          1.        MCASP Timing Conditions
          2.        MCASP Timing Requirements
          3.        243
          4.        MCASP Switching Characteristics
          5.        245
        11. 6.12.5.11 MCSPI
          1.        MCSPI Timing Conditions
          2.        MCSPI Timing Requirements - Controller Mode
          3.        249
          4.        MCSPI Switching Characteristics - Controller Mode
          5.        251
          6.        MCSPI Timing Requirements - Peripheral Mode
          7.        253
          8.        MCSPI Switching Characteristics - Peripheral Mode
          9.        255
        12. 6.12.5.12 MLB
          1.        MLB Timing Conditions
          2.        MLB Timing Requirements for MLBCLK - 3-pin
          3.        MLB Timing Requirements for Receive Data - 3-pin
          4.        MLB Switching Characteristics - 3-Pin
          5.        MLB Timing Requirements for MLBCLK - 6-pin
          6.        MLB Timing Requirements for Receive Data - 6-pin
          7.        MLB Switching Characteristics - 6-Pin
        13. 6.12.5.13 MMCSD
          1. 6.12.5.13.1 MMC0 - eMMC/SDIO Interface
            1.         MMC0 DLL Delay Mapping for SD/SDIO Timing Modes
            2.         MMC0 DLL Delay Mapping for eMMC Timing Modes
            3.         MMC Timing Conditions
            4.         MMC Timing Requirements - 3.3V Legacy SDR Mode
            5.         270
            6.         MMC Switching Characteristics - 3.3V Legacy SDR Mode
            7.         272
            8.         MMC Timing Requirements - 3.3V High Speed SDR Mode
            9.         274
            10.         MMC Switching Characteristics - 3.3V High Speed SDR Mode
            11.         276
            12.         MMC Timing Requirements - 1.8V Legacy SDR, UHS-I SDR12 Mode
            13.         278
            14.         MMC Switching Characteristics - 1.8V Legacy SDR, UHS-I SDR12 Mode
            15.         280
            16.         MMC Timing Requirements - 1.8V High Speed SDR, UHS-I SDR25 Mode
            17.         282
            18.         MMC Switching Characteristics - 1.8V High Speed SDR, UHS-I SDR25 Mode
            19.         284
            20.         MMC Switching Characteristics - UHS-I SDR50 Mode
            21.         286
            22.         MMC Switching Characteristics - UHS-I DDR50 Mode
            23.         288
            24.         MMC Switching Characteristics - HS200 Mode
            25.         290
        14. 6.12.5.14 OSPI
          1.        OSPI Timing Conditions
          2. 6.12.5.14.1 OSPI0 PHY Mode
            1. 6.12.5.14.1.1 OSPI0 With PHY Data Training
              1.          OSPI DLL Delay Mapping for PHY Data Training
              2.          OSPI Timing Requirements - PHY Data Training
              3.          297
              4.          OSPI Switching Characteristics - PHY Data Training
              5.          299
            2. 6.12.5.14.1.2 OSPI0 Without Data Training
              1. 6.12.5.14.1.2.1 OSPI0 PHY SDR Timing
                1.           OSPI DLL Delay Mapping for PHY SDR Timing Modes
                2.           OSPI Timing Requirements - PHY SDR Mode
                3.           304
                4.           OSPI Switching Characteristics - PHY SDR Mode
                5.           306
          3. 6.12.5.14.2 OSPI0 Tap Mode
            1. 6.12.5.14.2.1 OSPI0 Tap SDR Timing
              1.          OSPI Timing Requirements - Tap SDR Mode
              2.          310
              3.          OSPI Switching Characteristics - Tap SDR Mode
              4.          312
            2. 6.12.5.14.2.2 OSPI0 Tap DDR Timing
              1.          OSPI Timing Requirements - Tap DDR Mode
              2.          315
              3.          OSPI Switching Characteristics - Tap DDR Mode
              4.          317
        15. 6.12.5.15 Timers
          1.        Timer Timing Conditions
          2.        Timer Timing Requirements
          3.        Timer Switching Characteristics
          4.        322
        16. 6.12.5.16 UART
          1.        UART Timing Conditions
          2.        UART Timing Requirements
          3.        UART Switching Characteristics
          4.        327
        17. 6.12.5.17 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
      2. 7.2.2 Device/Power Manager
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.1.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.1.2 External Board Loopback
        3. 8.2.1.3 DQS (only available in Octal SPI devices)
      2. 8.2.2 USB VBUS Design Guidelines
      3. 8.2.3 System Power Supply Monitor Design Guidelines
      4. 8.2.4 High Speed Differential Signal Routing Guidance
      5. 8.2.5 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Table 5-48 Power Supply Signal Descriptions
SIGNAL NAME [1]SIGNAL TYPE [2]DESCRIPTION [3]ANJ PIN [4]
CAP_VDDS0PWRExternal capacitor connection for IO group 0L6
CAP_VDDS1PWRExternal capacitor connection for IO group 1F13
CAP_VDDS2PWRExternal capacitor connections for IO group 2R11
CAP_VDDS3PWRExternal capacitor connections for IO group 3H15
CAP_VDDS5PWRExternal capacitor connections for IO group 5P8
CAP_VDDS_CANUARTPWRExternal capacitor connection for IO group CANUARTE6
CAP_VDDS_MCUPWRExternal capacitor connection for IO group MCUE8
VDDA_1P8_USBPWRUSB 1.8V analog supplyP10
VDDA_3P3_USBPWRUSB 3.3V analog supplyR9
VDDA_ADC0PWRAnalog supply for ADCJ5
VDDA_CORE_USBPWRUSB core analog supplyN10
VDDA_MCUPWRMCU Analog supplyH7
VDDA_PLL0PWRAnalog supply for PLL0J9
VDDA_PLL1PWRAnalog supply for PLL1J10
VDDA_PLL2PWRAnalog supply for PLL2M11
VDDA_TEMP0PWRTEMP0 analog supplyK5
VDDA_TEMP1PWRTEMP1 analog supplyN11
VDDR_CANUARTPWRCore RAM supply for CANUART DomainE7
VDDR_COREPWRCore RAM supplyG10, H12, J8, K10, M10, M14, N12, N8
VDDSHV0PWRIO supply for IO group 0K6, M6
VDDSHV1PWRIO supply for IO group 1E13, F12
VDDSHV2PWRIO supply for IO group 2 P11, P12
VDDSHV3PWRIO supply for IO group 3H14, J14, K14
VDDSHV5PWRIO supply for IO group 5P9, R8
VDDSHV_CANUARTPWRIO supply for IO group CANUARTF7
VDDSHV_MCUPWRIO supply for IO group MCUF8, F9
VDDS_OSC0PWROscillator supplyF5
VDD_CANUARTPWRCore supply for CANUART DomainF6
VDD_COREPWRCore supplyG11, G14, G7, H10, H13, H9, J12, K13, K7, K9, L11, L12, L8, M13, M7, M9, P13, P7
VMON_1P8_SOCPWRVoltage monitor input for 1.8V SoC power supplyJ6
VMON_3P3_SOCPWRVoltage monitor input for 3.3V SoC power supplyH5
VMON_ER_VSYSPWRVoltage monitor input, fixed 0.45 V (+/-3%) threshold. Use with external precision voltage divider to monitor a higher voltage rail such as the PMIC input supply.H8
VPPPWRVPP supplyG5
VSSGNDGroundA1, A19, B2, C19, C3, D1, D11, D14, D19, D3, D4, D8, E10, E11, E12, E14, E15, E17, E18, E5, E9, F10, F11, F14, F15, F16, F4, G12, G13, G15, G4, G6, G8, G9, H11, H3, H6, J11, J13, J15, J7, K11, K12, K15, K8, L10, L13, L14, L15, L5, L7, L9, M12, M15, M5, M8, N13, N14, N15, N5, N6, N7, N9, P14, P15, P5, P6, R10, R12, R13, R14, R15, R5, R6, R7, T10, T16, T5, T8, T9, U10, U17, U4, U5, U8, V10, V18, V4, W1, W10, W19, W3, W6