SPRSPC5 May   2026 TMS320F28P551SG

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  IC Latch-Up Test: JESD78F.02
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Power Consumption Summary
      1. 6.6.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.6.2 System Current Consumption - VREG Disable - External Supply
      3. 6.6.3 Operating Mode Test Description
      4. 6.6.4 Current Consumption Graphs
      5. 6.6.5 Reducing Current Consumption
        1. 6.6.5.1 Typical Current Reduction per Disabled Peripheral
    7. 6.7  Electrical Characteristics
    8. 6.8  Special Considerations for 5V Fail-Safe Pins
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PN and PNA Packages
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Resistance Characteristics for YAF Package
    14. 6.14 Thermal Resistance Characteristics for ZNG Package
    15. 6.15 Thermal Design Considerations
    16. 6.16 System
      1. 6.16.1  Power Management Module (PMM)
        1. 6.16.1.1 Introduction
        2. 6.16.1.2 Overview
          1. 6.16.1.2.1 Power Rail Monitors
            1. 6.16.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.16.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.16.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.16.1.2.2 External Supervisor Usage
          3. 6.16.1.2.3 Delay Blocks
          4. 6.16.1.2.4 Internal VDD LDO Voltage Regulator (VREG)
          5. 6.16.1.2.5 VREGENZ
        3. 6.16.1.3 External Components
          1. 6.16.1.3.1 Decoupling Capacitors
            1. 6.16.1.3.1.1 VDDIO Decoupling
            2. 6.16.1.3.1.2 VDD Decoupling
        4. 6.16.1.4 Power Sequencing
          1. 6.16.1.4.1 Supply Pins Ganging
          2. 6.16.1.4.2 Signal Pins Power Sequence
          3. 6.16.1.4.3 Supply Pins Power Sequence
            1. 6.16.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.16.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.16.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.16.1.4.3.4 Supply Slew Rate
        5. 6.16.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.16.1.6 Power Management Module Electrical Data and Timing
          1. 6.16.1.6.1 Power Management Module Operating Conditions
          2. 6.16.1.6.2 Power Management Module Characteristics
      2. 6.16.2  Reset Timing
        1. 6.16.2.1 Reset Sources
        2. 6.16.2.2 Reset Electrical Data and Timing
          1. 6.16.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.16.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.16.2.2.3 Reset Timing Diagrams
      3. 6.16.3  Clock Specifications
        1. 6.16.3.1 Clock Sources
        2. 6.16.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.16.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.16.3.2.1.1 Input Clock Frequency
            2. 6.16.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.16.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.16.3.2.1.4 X1 Timing Requirements
            5. 6.16.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.16.3.2.1.6 APLL Characteristics
            7. 6.16.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.16.3.2.1.8 Internal Clock Frequencies
        3. 6.16.3.3 Input Clocks and PLLs
        4. 6.16.3.4 XTAL Oscillator
          1. 6.16.3.4.1 Introduction
          2. 6.16.3.4.2 Overview
            1. 6.16.3.4.2.1 Electrical Oscillator
              1. 6.16.3.4.2.1.1 Modes of Operation
                1. 6.16.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.16.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.16.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.16.3.4.2.2 Quartz Crystal
            3. 6.16.3.4.2.3 GPIO Modes of Operation
          3. 6.16.3.4.3 Functional Operation
            1. 6.16.3.4.3.1 ESR – Effective Series Resistance
            2. 6.16.3.4.3.2 Rneg – Negative Resistance
            3. 6.16.3.4.3.3 Start-up Time
              1. 6.16.3.4.3.3.1 X1/X2 Precondition
            4. 6.16.3.4.3.4 DL – Drive Level
          4. 6.16.3.4.4 How to Choose a Crystal
          5. 6.16.3.4.5 Testing
          6. 6.16.3.4.6 Common Problems and Debug Tips
          7. 6.16.3.4.7 Crystal Oscillator Specifications
            1. 6.16.3.4.7.1 Crystal Equivalent Series Resistance (ESR) Requirements
            2. 6.16.3.4.7.2 Crystal Oscillator Parameters
            3. 6.16.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.16.3.5 Internal Oscillators
          1. 6.16.3.5.1 INTOSC Characteristics
      4. 6.16.4  Flash Parameters
        1. 6.16.4.1 Flash Parameters 
      5. 6.16.5  RAM Specifications
      6. 6.16.6  ROM Specifications
      7. 6.16.7  Emulation/JTAG
        1. 6.16.7.1 JTAG Electrical Data and Timing
          1. 6.16.7.1.1 JTAG Timing Requirements
          2. 6.16.7.1.2 JTAG Switching Characteristics
          3. 6.16.7.1.3 JTAG Timing Diagram
        2. 6.16.7.2 cJTAG Electrical Data and Timing
          1. 6.16.7.2.1 cJTAG Timing Requirements
          2. 6.16.7.2.2 cJTAG Switching Characteristics
          3. 6.16.7.2.3 cJTAG Timing Diagram
      8. 6.16.8  GPIO Electrical Data and Timing
        1. 6.16.8.1 GPIO – Output Timing
          1. 6.16.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.16.8.1.2 General-Purpose Output Timing Diagram
        2. 6.16.8.2 GPIO – Input Timing
          1. 6.16.8.2.1 General-Purpose Input Timing Requirements
          2. 6.16.8.2.2 Sampling Mode
        3. 6.16.8.3 Sampling Window Width for Input Signals
      9. 6.16.9  Interrupts
        1. 6.16.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.16.9.1.1 External Interrupt Timing Requirements
          2. 6.16.9.1.2 External Interrupt Switching Characteristics
          3. 6.16.9.1.3 External Interrupt Timing
      10. 6.16.10 Low-Power Modes
        1. 6.16.10.1 Clock-Gating Low-Power Modes
        2. 6.16.10.2 Low-Power Mode Wake-up Timing
          1. 6.16.10.2.1 IDLE Mode Timing Requirements
          2. 6.16.10.2.2 IDLE Mode Switching Characteristics
          3. 6.16.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.16.10.2.4 STANDBY Mode Timing Requirements
          5. 6.16.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.16.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.16.10.2.7 HALT Mode Timing Requirements
          8. 6.16.10.2.8 HALT Mode Switching Characteristics
          9. 6.16.10.2.9 HALT Entry and Exit Timing Diagram
    17. 6.17 Analog Peripherals
      1. 6.17.1 Block Diagram
      2. 6.17.2 Analog Pins and Internal Connections
      3. 6.17.3 Analog Signal Descriptions
      4. 6.17.4 Analog-to-Digital Converter (ADC)
        1. 6.17.4.1 ADC Configurability
          1. 6.17.4.1.1 Signal Mode
        2. 6.17.4.2 ADC Electrical Data and Timing
          1. 6.17.4.2.1 ADC Operating Conditions
          2. 6.17.4.2.2 ADC Characteristics
          3. 6.17.4.2.3 ADC INL and DNL
          4. 6.17.4.2.4 ADC Performance Per Pin
          5. 6.17.4.2.5 ADC Input Model
          6. 6.17.4.2.6 ADC Timing Diagrams
      5. 6.17.5 Temperature Sensor
        1. 6.17.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.17.5.1.1 Temperature Sensor Characteristics
      6. 6.17.6 Comparator Subsystem (CMPSS)
        1. 6.17.6.1 CMPx_DACL
        2. 6.17.6.2 CMPSS Connectivity Diagram
        3. 6.17.6.3 Block Diagram
        4. 6.17.6.4 CMPSS Electrical Data and Timing
          1. 6.17.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.17.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.17.6.4.3 CMPSS Illustrative Graphs
          5. 6.17.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.17.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.17.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.17.7.1 Buffered DAC Electrical Data and Timing
          1. 6.17.7.1.1 Buffered DAC Operating Conditions
          2. 6.17.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.17.8 Programmable Gain Amplifier (PGA)
        1. 6.17.8.1 PGA Electrical Data and Timing
          1. 6.17.8.1.1 PGA Operating Conditions
          2. 6.17.8.1.2 PGA Characteristics
    18. 6.18 Control Peripherals
      1. 6.18.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.18.1.1 Control Peripherals Synchronization
        2. 6.18.1.2 ePWM Electrical Data and Timing
          1. 6.18.1.2.1 ePWM Timing Requirements
          2. 6.18.1.2.2 ePWM Switching Characteristics
          3. 6.18.1.2.3 Trip-Zone Input Timing
            1. 6.18.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.18.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.18.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.18.2.1 HRPWM Electrical Data and Timing
          1. 6.18.2.1.1 High-Resolution PWM Characteristics
      3. 6.18.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.18.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.18.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.18.4 Enhanced Capture (eCAP)
        1. 6.18.4.1 eCAP Block Diagram
        2. 6.18.4.2 eCAP Synchronization
        3. 6.18.4.3 eCAP Electrical Data and Timing
          1. 6.18.4.3.1 eCAP Timing Requirements
          2. 6.18.4.3.2 eCAP Switching Characteristics
      5. 6.18.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.18.5.1 eQEP Electrical Data and Timing
          1. 6.18.5.1.1 eQEP Timing Requirements
          2. 6.18.5.1.2 eQEP Switching Characteristics
      6. 6.18.6 Sigma-Delta Filter Module (SDFM)
        1. 6.18.6.1 SDFM Electrical Data and Timing
          1. 6.18.6.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
          2. 6.18.6.1.2 SDFM Electrical Data and Timing (Using ASYNC)
          3. 6.18.6.1.3 SDFM Timing Requirements When Using Asynchronous GPIO - ASYNC - Option
          4. 6.18.6.1.4 SDFM Timing Requirements When Using Synchronous GPIO SYNC Option
          5. 6.18.6.1.5 SDFM Timing Diagram
    19. 6.19 Communications Peripherals
      1. 6.19.1 Modular Controller Area Network (MCAN)
      2. 6.19.2 Inter-Integrated Circuit (I2C)
        1. 6.19.2.1 I2C Electrical Data and Timing
          1. 6.19.2.1.1 I2C Timing Requirements
          2. 6.19.2.1.2 I2C Switching Characteristics
          3. 6.19.2.1.3 I2C Timing Diagram
      3. 6.19.3 Power Management Bus (PMBus) Interface
        1. 6.19.3.1 PMBus Electrical Data and Timing
          1. 6.19.3.1.1 PMBus Electrical Characteristics
          2. 6.19.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.19.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.19.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.19.4 Serial Communications Interface (SCI)
      5. 6.19.5 Serial Peripheral Interface (SPI)
        1. 6.19.5.1 SPI Controller Mode Timings
          1. 6.19.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.19.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.19.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.19.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.19.5.2 SPI Peripheral Mode Timings
          1. 6.19.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.19.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.19.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.19.6 Local Interconnect Network (LIN)
      7. 6.19.7 Fast Serial Interface (FSI)
        1. 6.19.7.1 FSI Transmitter
          1. 6.19.7.1.1 FSITX Electrical Data and Timing
            1. 6.19.7.1.1.1 FSITX Switching Characteristics
            2. 6.19.7.1.1.2 FSITX Timings
        2. 6.19.7.2 FSI Receiver
          1. 6.19.7.2.1 FSIRX Electrical Data and Timing
            1. 6.19.7.2.1.1 FSIRX Timing Requirements
            2. 6.19.7.2.1.2 FSIRX Switching Characteristics
            3. 6.19.7.2.1.3 FSIRX Timings
        3. 6.19.7.3 FSI SPI Compatibility Mode
          1. 6.19.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.19.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.19.7.3.1.2 FSITX SPI Signaling Mode Timings
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2.     TAPE AND REEL INFORMATION
    3.     TRAY

Abstract

PACKAGING INFORMATION

Orderable part number Status(1) Material
type(2)		 Package | Pins Package qty | Carrier RoHS(3) Lead finish/
Ball material(4)		 MSL rating/Peak reflow(5) Op temp (°C) Part marking(6)
F28P558SG5PZRQ1  Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG5PZQ
F28P558SG5PZQ1  Preview Production LQFP (PZ) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG5PZQ
F28P558SG3PZRQ1 Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG3PZQ
F28P558SG2PZRQ1 Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG2PZQ
F28P558SG5PNARQ1  Preview Production LQFP (PNA) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG5PNAQ
F28P558SG5PNAQ1  Preview Production LQFP (PNA) | 80 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG5PNAQ
F28P558SG3PNARQ1 Preview Production LQFP (PNA) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG3PNAQ
F28P558SG2PNARQ1 Preview Production LQFP (PNA) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG2PNAQ
F28P558SG5PMRQ1  Preview Production LQFP (PM) | 64 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG5PMQ
F28P558SG5PMQ1  Preview Production LQFP (PM) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG5PMQ
F28P558SG3PMRQ1 Preview Production LQFP (PM) | 64 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG3PMQ
F28P558SG2PMRQ1 Preview Production LQFP (PM) | 64 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P558SG2PMQ
F28P551SG5PZ Active Preproduction LQFP (PZ) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551
SG5PZ
F28P551SG5PZR Active Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PZ
F28P552SG4PZR Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SG4PZ
F28P552SG3PZR Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SG3PZ
F28P551SD5PZR Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SD5PZ
F28P552SD3PZR Preview Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SD3PZ
XF28P551SG5PNR Active Preproduction LQFP (PN) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PN
XF28P551SG5PN Active Preproduction LQFP (PN) | 80 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PN
F28P551SG5PNR Preview Production LQFP (PN) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PN
F28P551SG5PN Preview Preproduction LQFP (PN) | 80 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PN
F28P552SG4PNR Preview Production LQFP (PN) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SG4PN
F28P552SG3PNR Preview Production LQFP (PN) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SG3PN
F28P551SD5PNR Preview Production LQFP (PN) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SD5PN
F28P552SD3PNR Preview Production LQFP (PN) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SD3PN
XF28P551SG5PNAR Active Preproduction LQFP (PNA) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PNA
XF28P551SG5PNA Active Preproduction LQFP (PNA) | 80 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PNA
F28P551SG5PNAR Preview Production LQFP (PNA) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PNA
F28P551SG5PNA Preview Preproduction LQFP (PNA) | 80 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PNA
F28P552SG4PNAR Preview Production LQFP (PNA) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P552SG4PNA
XF28P551SG5PMR Active Production LQFP (PM) | 64 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PM
XF28P551SG5PM Active Preproduction LQFP (PM) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PM
F28P551SG5PMR Preview Production LQFP (PM) | 64 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PM
F28P551SG5PM Preview Production LQFP (PM) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5PM
F28P551SD5PMR Preview Production LQFP (PM) | 64 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SD5PM
XF28P551SG5RSHR Active Preproduction VQFN (RSH) | 56 4000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5RSH
F28P551SG5RSHR Preview Production VQFN (RSH) | 56 4000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5RSH
F28P551SD5RSHR Preview Production VQFN (RSH) | 56 4000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SD5RSH
XF28P551SG5YAFR Active Preproduction WCSP (YAF) | 49 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM −40 to 125 F28P551SG5YAF
F28P551SG5YAFR Preview Production WCSP (YAF) | 49 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM −40 to 125 F28P551SG5YAF
XF28P551SG5ZNG Preview Preproduction VQFN (ZNG) | 32 490 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5ZNG
F28P551SG5ZNG Preview Production VQFN (ZNG) | 32 490 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR −40 to 125 F28P551SG5ZNG
(1) Status: For more details on status, see our product life cycle.
(2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.
(5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.