SPRUIW3 October   2021 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Trademarks
  2. 1Feature Differences Between F28004x and F28003x
    1. 1.1 F28004x and F28003x Feature Comparison
  3. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ Package
      1. 2.1.1 100-Pin PZ Migration for Existing PCB
      2. 2.1.2 100-Pin PZ Migration for New PCB Design
    2. 2.2 PCB Hardware Changes for the 64-Pin PM Package
      1. 2.2.1 64-Pin PM Migration for New and Existing PCB
  4. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28003x
      1. 3.1.1  TMU Type1
      2. 3.1.2  Fast Integer Division (FINTDIV)
      3. 3.1.3  Host Interface Controller (HIC)
      4. 3.1.4  Background CRC (BGCRC)
      5. 3.1.5  Standby Low Power Mode
      6. 3.1.6  X1 GPIO Functionality
      7. 3.1.7  Diagnostic Features (PBIST/HWBIST)
      8. 3.1.8  Advance Encryption Standard (AES)
      9. 3.1.9  Secure Boot/JTAG Lock
      10. 3.1.10 Modular Controller Area Network (MCAN)
      11. 3.1.11 Embedded Pattern Generator (EPG)
      12. 3.1.12 Live Firmware Update (LFU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 XTAL Module
      2. 3.5.2 PLL
      3. 3.5.3 PIE Channel Mapping
      4. 3.5.4 Bootrom
      5. 3.5.5 CLB and Motor Control Libraries
      6. 3.5.6 ERAD
      7. 3.5.7 GPIO
      8. 3.5.8 AGPIO
      9. 3.5.9 ERROR Status
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 DCDC
      3. 3.6.3 POR/BOR
      4. 3.6.4 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  5. 4Application Code Migration From F28004x to F28003x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 Minimum Compiler Version Requirement for TMU Type 1
    4. 4.4 C2000Ware Examples
  6. 5Specific Use Cases Related to F28003x New Features
    1. 5.1 HIC
    2. 5.2 FINTDIV
    3. 5.3 TMU Type1
    4. 5.4 AES
    5. 5.5 MCAN
    6. 5.6 EPG
  7. 6EABI Support
    1. 6.1 Flash API
    2. 6.2 NoINIT Struct Fix (Linker Command)
    3. 6.3 Pre-Compiled Libraries
  8. 7References

2.2.1 64-Pin PM Migration for New and Existing PCB

Table 2-3 outlines the migration moving from F28004x/F28003x to F28003x/F28004x, respectively.

For the color legend, see Figure 2-3 and Figure 2-4.

Table 2-3 64-Pin PM Migration Between F28004x and F28003x For New and Existing PCB
Pin No Pin Name Transition Type Action
F28004x F28003x F28003x to F28004x F28004x to F28003x
Minor Incompatibility - Signals in Common (1)
6 A6, PGA5_OF A6 Common Analog Channel Use A6
7 B2, C6, PGA3_OF B2, C6 Use B2 or C6
8 B3, VDAC A3, B3, C5 VDAC Use B3 or VDAC
9 A2, B6, PGA1_OF A2, B6, C9 Use A2 or B6
11 PGA5_IN, C4 A14, B14, C4 Use C4
12 PGA1_IN, C0 A11, B10, C0 Use C0
13 PGA3_IN, C2 A5, B12, C2 Use C2
14 A1, DACB_OUT A1, B7, DACB_OUT Use A1 or DACB_OUT
18 C1 A12, C1 Use C1
19 PGA4_IN, C3 A7, C3 Use C3
23 C14 A4, B8, C14 Use C14
24 B4, C8 A9, B4, C8 Use B4 or C8
42 X1 GPIO19, X1 Common Clock GPIO19 not available for use
54 GPIO23_VSW GPIO23 Common GPIO Do not use DCDC. GPIO22 & GPIO23 available for use
56 GPIO22_VFBSW GPIO22
Major Incompatibility - Different Signals and Types
10 PGA1_GND, PGA3_GND, PGA5_GND A15, B9, C7 PGA Ground to ADC Channel Tie to VSS
20 PGA2_GND, PGA4_GND, PGA6_GND A8, B0, C11
55 VSS_SW GPIO41 Ground to GPIO Tie to VSS through 0-Ohm resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIO
53 VDDIO_SW GPIO40 Power to GPIO Tie to VDDIO through 0-Ohm resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIO
(Non-Q Variant) Major Incompatibility - Different Signals and Types
46 VREGENZ GPIO39 External VREG not supported. Tie to VSS through 0-Ω resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIO
(Q Variant) Major Incompatibility - Different Signals and Types
29 FLT2 GPIO13 Flash Test Pins to GPIO No connect. Enable internal pull-up for the GPIOs on F28003x
30 FLT1 GPIO12
  1. Channel to use selected in software.