SPRUIY9C May   2021  – December 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
  6. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 Important Usage Notes
    3. 2.3 System Description
      1. 2.3.1 Functional Block Diagram
      2. 2.3.2 Power-On/Off Procedures
        1. 2.3.2.1 Power-On Procedure
        2. 2.3.2.2 Power-Off Procedure
      3. 2.3.3 Peripheral and Major Component Description
        1. 2.3.3.1  Clocking
          1. 2.3.3.1.1 Ethernet PHY Clock
          2. 2.3.3.1.2 AM64x SoC Clock
        2. 2.3.3.2  Reset
        3. 2.3.3.3  Power
          1. 2.3.3.3.1 Power Input
          2. 2.3.3.3.2 USB Type-C Interface for Power Input
          3. 2.3.3.3.3 Power Fault Indication
          4. 2.3.3.3.4 Power Supply
          5. 2.3.3.3.5 Power Sequencing
          6. 2.3.3.3.6 Power Supply
        4. 2.3.3.4  Configuration
          1. 2.3.3.4.1 Boot Modes
        5. 2.3.3.5  JTAG
        6. 2.3.3.6  Test Automation
        7. 2.3.3.7  UART Interface
        8. 2.3.3.8  Memory Interfaces
          1. 2.3.3.8.1 LPDDR4 Interface
          2. 2.3.3.8.2 MMC Interface
            1. 2.3.3.8.2.1 Micro SD Interface
            2. 2.3.3.8.2.2 WiLink Interface
            3. 2.3.3.8.2.3 OSPI Interface
            4. 2.3.3.8.2.4 Board ID EEPROM Interface
        9. 2.3.3.9  Ethernet Interface
          1. 2.3.3.9.1 DP83867 PHY Default Configuration
          2. 2.3.3.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs
          3. 2.3.3.9.3 Industrial Application LEDs
        10. 2.3.3.10 USB 3.0 Interface
        11. 2.3.3.11 PRU Connector
        12. 2.3.3.12 User Expansion Connector
        13. 2.3.3.13 MCU Connector
        14. 2.3.3.14 Interrupt
        15. 2.3.3.15 I2C Interface
        16. 2.3.3.16 IO Expander (GPIOs)
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 Regulatory Compliance
  9. 5Additional Information
    1. 5.1 Known Issues
      1. 5.1.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1
      2. 5.1.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V
      3. 5.1.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements
      4. 5.1.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions
      5. 5.1.5 Issue 5 - Junk Character
      6. 5.1.6 Issue 6 - Test Power Down Signal Floating
      7. 5.1.7 Issue 7 - uSD Boot Not Working
    2.     Trademarks
    3.     65
  10. 6Revision History
2.3.3.3.6 Power Supply

The SoC Core voltage (VDD_CORE) of the AM64x SoC is set to 0.75V. SoC Array Core Voltage (VDDR_CORE) and other array core voltages (VDDA_0P85_SERDES0_C, VDDA_0P85_SERDES0, VDDA_0P85_USB0, VDD_DLL_MMC0 and VDD_MMC0) are configured to 0.85V and are supplied through a common rail.

The SoC has different IO groups. Each IO group is powered by specific power supplies as given in Table 2-8.

Table 2-8 SoC Power Supply
SI.No Power Supply SoC Supply Rails IO Power Group Power
1 VDDAR_CORE VDDA_0P85_SERDES0 SERDES0 0.85
VDDA_0P85_SERDES0_C 0.85
VDDA_0P85_USB0 USB0 0.85
VDD_MMC0 MMC0 0.85
VDDR_CORE CORE 0.85
2 SoC_DVDD3V3 VDDSHV_MCU MCU 3.3
VDDA_3P3_USB0 USB0 3.3
VDDSHV0 General 3.3
VDDSHV1 PRG0 3.3
VDDSHV2 PRG1 3.3
VDDSHV3 GPMC 3.3
VMON_3P3_MCU 3.3
VMON_3P3_SOC 3.3
3 VDDA_1V8_MCU VDDA_MCU MCU 1.8
4 VDDA_1V8_SERDES VDDA_1P8_SERDES0 SERDES0 1.8
5 VDDA_1V8_USB0 VDDA_1P8_USB0 USB0 1.8
6 VDDA_1V8 VDDS_OSC OSC0 1.8
VDDA_TEMP_0/1 1.8
VDDA_PLL_0/1/2 1.8
7 VDDS_DDR VDDS_DDR DDR0 1.1
VDDS_DDR_C 1.1
8 SOC_DVDD1V8 VDDSHV4 FLASH 1.8
VDDS_MMC0 MMC0 1.8
VMON_1P8_MCU 1.8
VMON_1P8_SOC 1.8
9 VDDSHV_SD_IO VDDSHV5 MMC1 3.3
10 VDDS_MMC0/ADC0_VREFP VDDS_MMC0 MMC0 0