SPRUJ62 December   2022 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

2.4.6 Automation and Control Connector [J50]

The EVM supports an interface to allow for automated control of the system, including functions like on/off, reset, and boot mode settings.

Table 2-18 Test Automation Interface Pin Definition [J50]
Pin # Pin Name Description Dir
1 Power Power, 3.3 V Output
2 Power Power, 3.3 V Output
3 Power Power, 3.3 V Output
4-6 <open>
7 GND Ground
8-15 <open>
16 GND Ground
17-24 <open>
25 GND Ground
26 POWERDOWNz EVM Power Down Input
27 PORz EVM Power-On/Cold Reset (MCU_PORz) Input
28 RESETz EVM Warm Reset (RESETz) Input
29 <open>
30 INT1z EXTINT / GPIO0_0 Input
31 INT2z WKUP_GPIO0_7 Bi-Dir
32 <open>
33 BOOTMODE_RSTz Bootmode Buffer Reset Input
34 GND Ground
35 <open>
36 Bus #1 I2C_SCL INA Bus #1 I2C (optional connection to Processor I2C1) Bi-Dir
37 Bus #2 I2C_SCL INA Bus #2 I2C Input
38 Bus #1 I2C_SDA INA Bus #1 I2C (optional connection to Processor I2C1) Bi-Dir
39 Bus #2 I2C_SDA INA Bus #2 I2C Bi-Dir
40 GND Ground
41 GND Ground
42 GND Ground
Note: In the DIR, column, output is to the test automation controller, input is from the automation controller. Bi-Dir signals can be configured as either input or output.
Note: The Signal polarity is defined with a trailing 'z' in the Pin Name, which indicates the signal is active LOW. For example, POWERDOWNz is an active low signal, meaning '0' = EVM is Powered Down, '1' = EVM is NOT Powered Down.