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AM69

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General Purpose octal core 64-bit Arm Cortex-A72 with graphics, PCIe Gen 3, Ethernet, USB 3.0

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AM69

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Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, Display subsystem, MIPI DPI Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator Features General purpose, USB 3.0 Operating system Linux Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Catalog Operating temperature range (°C) -40 to 105
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, Display subsystem, MIPI DPI Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator Features General purpose, USB 3.0 Operating system Linux Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BXS-4-64, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES 

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BXS-4-64, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES 

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The AM69 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69 class of processors.

The AM69 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69 class of processors.
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Technical documentation

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* Data sheet AM69x Processors, Silicon Revision 1.0 datasheet (Rev. A) PDF | HTML 18 Aug 2023
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. A) PDF | HTML 20 May 2023
* User guide J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. C) PDF | HTML 11 Aug 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SK-AM69 — Starter kit for Sitara™ processors

The SK-AM69 Starter Kit/Evaluation Module (EVM) is based on the AM69x AI vision processor which includes an image signal processor (ISP) supporting up to 1440MP/s, 32 tera-operations-per-second (TOPS) AI accelerator, eight 64-bit Arm®-Cortex® A72 microprocessor, and H.264/H.265 video (...)

User guide: PDF | HTML
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Software development kit (SDK)

PROCESSOR-SDK-LINUX-AM69 — Processor SDK Linux for AM69

The AM69 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM69 — General Purpose octal core 64-bit Arm Cortex-A72 with graphics, PCIe Gen 3, Ethernet, USB 3.0
Hardware development
Evaluation board
SK-AM69 — Starter kit for Sitara™ processors
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IDE, configuration, compiler or debugger

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Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

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Products
Automotive mmWave radar sensors
AWR1243 — 76-GHz to 81-GHz high-performance automotive MMIC AWR1443 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating MCU and hardware accelerator AWR1642 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP and MCU AWR1843 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR1843AOP — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 — 76-GHz to 81-GHz automotive second-generation high-performance MMIC AWR2944 — Automotive 2nd-generation, 76-GHz to 81-GHz, high-performance SoC for corner and long-range radar AWR6443 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR6843AOP — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating antenna on package, DSP and MCU
Industrial mmWave radar sensors
IWR1443 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 — Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR6443 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP)
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Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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