Processor cores:
Multimedia:
Memory subsystem:
Device security:
High speed serial interfaces:
Ethernet
Automotive interfaces:
Audio interfaces:
Flash memory interfaces:
System-on-Chip (SoC) architecture:
TPS6594-Q1 Companion Power Management ICs (PMIC):
The AM69, AM69A scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.
The AM69, AM69A provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.
General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.
Key Performance Cores Overview: The C7000™ DSP next generation core (C7™) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMAv2” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7/MMA cores are available only for deep-learning function in the AM69, AM69A class of processors.
TI does not offer direct design support for this device. For the best available options while working through your design, contact Toradex.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | AM69x Processors, Silicon Revision 1.0 datasheet (Rev. F) | PDF | HTML | Aug 17, 2026 |
| * | User guide | J784S4 J742S2 Technical Reference Manual (Rev. E) | PDF | HTML | Sep 9, 2025 |
| * | Errata | J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. C) | PDF | HTML | Jun 12, 2026 |
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