SPRZ439H January   2017  – February 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   TMS320F28004x Real-Time MCUs Silicon Errata (Silicon Revisions B, A, 0)
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 FPU32 and VCU Back-to-Back Memory Accesses
      3. 3.1.3 Caution While Using Nested Interrupts
      4. 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17. 3.2.1 Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22. 3.2.2 Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28. 3.2.3 Advisory
      29.      Advisory
      30.      Advisory
      31. 3.2.4 Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

Advisory

Analog Trim of Some TMX Devices

Revisions Affected

0, A

Details

Some TMX samples may not have analog trims programmed. This could degrade the performance of the ADC, buffered DAC, internal oscillators, PGA, and internal voltage regulator. A value of all zeros in these trim registers will have the following impact.

TRIM REGISTER IMPACT OF TRIM VALUE EQUAL TO ZERO
ADC offset AdcaRegs.ADCOFFTRIM Degraded performance of the ADC offset error specification.
AdcbRegs.ADCOFFTRIM
AdccRegs.ADCOFFTRIM
ADC reference AnalogSubsysRegs.ANAREFTRIMA Degraded performance of the ADC for all specifications. No workaround available.
AnalogSubsysRegs.ANAREFTRIMB
AnalogSubsysRegs.ANAREFTRIMC
ADC linearity AdcaRegs.ADCINLTRIM2-3 Degraded INL and DNL specifications of the ADC. No workaround available.
AdcbRegs.ADCINLTRIM2-3
AdccRegs.ADCINLTRIM2-3
Internal oscillator AnalogSubsysRegs.INTOSC1TRIM Degraded frequency accuracy and temperature drift of the internal oscillators.
AnalogSubsysRegs.INTOSC2TRIM
Buffered DAC offset DacaRegs.DACTRIM Degraded offset error specification of the buffered DAC. No workaround available.
DacbRegs.DACTRIM
PGA gain and offset PGAGAIN3TRIM Degraded performance of the PGA gain and offset error specifications. No workaround available.
PGAGAIN6TRIM
PGAGAIN12TRIM
PGAGAIN24TRIM

Workarounds

The following workarounds can be used for improved performance, though it still may not meet data sheet specifications.

Missing ADC offset trim can be generated by following the instructions in the ADC Zero Offset Calibration section of the TMS320F28004x Real-Time Microcontrollers Technical Reference Manual.

If the internal oscillator trim contains all zeros, the user can adjust the lowest 10 bits of the oscillator trim register between 1 (minimum) and 1023 (maximum) while observing the system clock on the XCLOCKOUT pin.