Details:

The ADCINT flag can be set before the ADCRESULT value is latched (see the tLAT and tINT(LATE) columns in the ADC Timings tables of the AM263x Technical Reference Manual).

The DMA can read the ADCRESULT value as soon as 3 cycles after the ADCINT trigger is set. As a result, the DMA could read a prior ADCRESULT value when the user expects the latest result if all of the following are true:

• The ADC is in late interrupt mode.
• The ADC operates in a mode where tINT (LATE) occurs 3 or more cycles before tLAT (ADCCTL2 [PRESCALE] > 2 for 12-bit mode).
• The DMA is triggered from the ADCINT signal.
• The DMA immediately reads the ADCRESULT value associated with that ADCINT signal without reading any other values first.
• The DMA was idle when it received the ADCINT trigger.

Only the DMA reads listed above could result in reads of stale data; the following non-DMA methods will always read the expected data:

• The ADCINT flag triggers a CLA task.
• The ADCINT flag triggers a CPU ISR.
• The CPU polls the ADCINT flag.

Workaround(s):

Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy transaction. This will result in enough delay that the second channel will always read the fresh ADC result.