SPRZ488F March   2022  – May 2026 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
  3. 2Silicon Usage Notes
    1.     i2324
    2.     i2348
    3.     i2364
    4.     i2508
  4. 3Silicon Advisories
    1.     i2310
    2.     i2311
    3.     i2313
    4.     i2329
    5.     i2345
    6.     i2346
    7.     i2347
    8.     i2349
    9.     i2350
    10.     i2352
    11.     i2353
    12.     i2354
    13.     i2355
    14.     i2356
    15.     i2357
    16.     i2358
    17.     i2359
    18.     i2374
    19.     i2375
    20.     i2386
    21.     i2392
    22.     i2393
    23.     i2394
    24.     i2395
    25.     i2401
    26.     i2402
    27.     i2403
    28.     i2404
    29.     i2405
    30.     i2427
    31.     i2428
    32.     i2433
    33.     i2438
    34.     i2439
    35.     i2488
    36.     i2499
    37.     i2500
    38.     i2502
    39.     i2503
  5.   Trademarks
  6. 4Revision History

i2488


CLOCKS : PLL Cofiguration for presice 50-50 Duty cycle clocks

Details:

The VCO within a PLL can generate output waveforms with varying duty cycles, which can not meet the requirement for a precise 50-50 duty cycle needed by system & peripherals.

Severity:

Minor

Workaround(s):

Configure the PLL to operate at twice (2x) the target frequency. Configure the clock divider (HSDIVIDER) register to divide the PLL output by 2.