SPRZ506E October   2022  – July 2025 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts With Repeat Block
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8. 3.2.1 Advisory
      9.      Advisory
      10. 3.2.2 Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16. 3.2.4 Advisory
      17.      Advisory
      18. 3.2.5 Advisory
      19.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
  7. 5Silicon Revision A Usage Notes and Advisories
    1. 5.1 Silicon Revision A Usage Notes
    2. 5.2 Silicon Revision A Advisories
  8. 6Silicon Revision 0 Usage Notes and Advisories
    1. 6.1 Silicon Revision 0 Usage Notes
    2. 6.2 Silicon Revision 0 Advisories
  9. 7Documentation Support
  10. 8Trademarks
  11. 9Revision History

3.1.2 Caution While Using Nested Interrupts With Repeat Block

Revisions Affected: 0, A, B, C

If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order to use the nesting feature, then the user must disable the interrupts before exiting the ISR by using the DINT assembly instruction. Failing to do so may cause the bits in the RB register to not be restored correctly, resulting in undefined code behavior.

If the RPTB ASM instruction is not used inside the application, then there is no issue. In the case of C code source, analysis of the generated disassembly would need to be performed to verify this.

If the ISR is coded in C, then the C28x C compiler may take care of the above and no action is required. If the ISR is coded in C28x assembly language, then the above guidance must be followed.

Note:

CGT v15.12.2.LTS (released in April 2016) or newer CGT packages addresses this requirement automatically. DINT only needs to be added for earlier revisions of the CGT tools.