SPRZ506E October   2022  – July 2025 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts With Repeat Block
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8. 3.2.1 Advisory
      9.      Advisory
      10. 3.2.2 Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16. 3.2.4 Advisory
      17.      Advisory
      18. 3.2.5 Advisory
      19.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
  7. 5Silicon Revision A Usage Notes and Advisories
    1. 5.1 Silicon Revision A Usage Notes
    2. 5.2 Silicon Revision A Advisories
  8. 6Silicon Revision 0 Usage Notes and Advisories
    1. 6.1 Silicon Revision 0 Usage Notes
    2. 6.2 Silicon Revision 0 Advisories
  9. 7Documentation Support
  10. 8Trademarks
  11. 9Revision History

Advisory

CMPSS: A CMPSS Glitch can Occur if Comparator Input Pin has AGPIO Functionality and ADC is Sampling the Input Pin

Revisions Affected

0, A, B, C

Details

The combinations of use cases for a specific analog input pin that need special considerations are shown in Table 3-2. As shown in this table, special considerations or workarounds need to be used for the combination of CMPSS Input, ADC Sampling, and AGPIO.

Table 3-2 Combinations of Use Cases for a Specific Analog Input Pin
FUNCTION USED ON A SPECIFIC ANALOG PIN COMPONENT USED
CMPSS Comparator Input Yes - Yes - Yes
ADC Sampling Yes Yes - Yes Yes
AGPIO Analog Pin Type Yes Yes Yes - -
AIO Analog Pin Type - - - Yes Yes
Result Workaround needed No special analysis or workaround needed

The AGPIO analog pin path contains an extra series switch of 53Ω. This creates a low-capacitance isolated node shared by the ADC and CMPSS comparator, as shown in Figure 3-1. This node can be disturbed when the ADC samples the channel (depending on the prior voltage stored on the ADC sample-and-hold capacitor), and this disturbance can cause a false CMPSS event of up to 50ns. To accommodate this potential disturbance, the workarounds below can be implemented.

TMS320F2800137 TMS320F2800135 TMS320F2800133 TMS320F2800132 Analog Subsystem Diagram with AGPIO and AIO Analog Pin Types Figure 3-1 Analog Subsystem Diagram with AGPIO and AIO Analog Pin Types

Workarounds

  1. Use a different pin (that is AIO pin type) for analog channels that need both ADC and CMPSS together.
  2. Use the CMPSS Digital Filter with a setting of 50ns or greater, which will filter the temporary disturbance.
  3. Precondition the sample-and-hold capacitor of the ADC so that the disturbance will not cause a false trip. For example, perform a dummy read of a 3.3V connection from a different channel on the ADC immediately before the impacted channel is read, so the disturbance is in the positive direction, away from the false trip. The opposite dummy read of a 0V signal would be used if the false trip is inverted in polarity.