SPRZ580A December 2024 – October 2025 AM62D-Q1
Table 1-1 lists all usage notes and the applicable silicon revision(s). Table 1-2 lists all advisories, modules affected, and the applicable silicon revision(s).
| MODULE | DESCRIPTION | SILICON REVISIONS AFFECTED |
|---|---|---|
| AM62Dx 1.0 | ||
| Boot | i2372 — ROM doesn't support select multi-plane addressing schemes in Serial NAND boot | YES |
| DDR | i2330 — DDRSS Register Configuration Tool Updates | YES |
| OSPI | i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash | YES |
| MODULE | DESCRIPTION | SILICON REVISIONS AFFECTED |
|---|---|---|
| AM62Dx 1.0 | ||
| BCDMA | i2431 — BCDMA: RX Channel can lockup in certain scenarios | YES |
| BCDMA | i2436 — BCDMA: BCDMA RX_IGNORE_LONG setting in RX CHAN CFG register doesn't work | YES |
| Boot | i2366 — Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operation | YES |
| Boot | i2371 — Boot: ROM code may hang in UART boot mode during data transfer | YES |
| Boot | i2410 — Boot: ROM may fail to boot due to i2409 | YES |
| Boot | i2413 — Boot: HS-FS ROM boots corrupted ROM boot image | YES |
| Boot | i2414 — Boot: Ethernet PHY Scan and Bring-Up Flow doesn't work with PHYs that don't support Auto Negotiation | YES |
| Boot | i2417 — Boot: GPMC NAND configured to slower clock speed | YES |
| Boot | i2419 — Boot: When disabling deskew calibration, ROM does not check if deskew calibration was enabled | YES |
| Boot | i2420 — Boot: XSPI Boot time is not consistent in SFDP mode | YES |
| Boot | i2421 — Boot: fatTiny GPT handling causes data abort | YES |
| Boot | i2422 — Boot: ROM timeout for MMCSD filesystem boot too long | YES |
| Boot | i2423 — Boot: HS-FS ROM applies debug access restrictions to all address space covered by the efuse controller firewall | YES |
| Boot | i2435 — Boot: ROM timeout for eMMC boot too long | YES |
| Boot | i2482 — Boot: ROM does not provide enough clocks during SD card initialization | YES |
| Boot | i2464 — Boot: ROM is unable to boot from SD cards with incorrect formatting | YES |
| C7x | i2199 — C71x: SE returning incorrect data when non-aligned transposed stream crosses AM1 circular buffer boundary | YES |
| C7x | i2120 — C71x: SE returning incorrect data when non-aligned transposed stream crosses AM1 circular buffer boundary | YES |
| C7x | i2087— C7x MMA HWA_STATUS reports errors before application starts | |
| C7x | i2376 — C7x: SE/SA/HWAOPEN receives corrupted template following two back to back VPUT/MVC instructions | YES |
| C7x | i2399 — C7x: CPU NLC Module Not Clearing State on Interrupt | YES |
| CPSW | i2208 — CPSW: ALE IET Express Packet Drops | YES |
| CPSW | i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up | YES |
| DDR | i2160 — DDR: Valid VRef range must be defined during LPDDR4 Command Bus Training | YES |
| ECC_AGGR | i2049 — ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending ECC Aggregator Interrupts | YES |
| Interrupt Aggregator | i2196 — IA: Potential deadlock scenarios in IA | YES |
| LPM | i2487 — LPM: Low power modes may inadvertently corrupt DDR contents | YES |
| MCAN | i2278 — MCAN: Message Transmit order is not ensured from dedicated Tx Buffers configured with same Message ID | YES |
| MCAN | i2279 — MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID | YES |
| MMCHS | i2312 — MMCHS HS200 and SDR104 Command Timeout Window Too Small | YES |
| MMCHS | i2493 — MMCSD: HS200 Write Failures | YES |
| OSPI | i2189 — OSPI: Controller PHY Tuning Algorithm | YES |
| OSPI | i2249 — OSPI: Failing OSPI DDR PHY Internal Pad Loopback and No Loopback timing modes | YES |
| OSPI | i2383 — OSPI: 2-byte address is not supported in PHY DDR mode | YES |
| PRG | i2253 — PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure | YES |
| PSIL | i2137 — PSIL: Clock stop operation can result in undefined behavior | YES |
| RAT | i2062 — RAT: Error Interrupt Triggered Even When Error Logging Disable Is Set | YES |
| RESET | i2407 — RESET: MCU_RESETSTATz unreliable when MCU_RESETz is asserted low | YES |
| USART | i2310 — USART: Erroneous triggering of timeout interrupt | YES |
| USART | i2311 — USART Spurious DMA Interrupts | YES |
| USB | i2134 — USB: 2.0 Compliance Receive Sensitivity Test Limitation | YES |
| USB | i2409 — USB: USB2 PHY locks up due to short suspend | YES |