SPVA024A June   2025  – October 2026 ADC810-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  POR
    6. 5.6  Timing Characteristics
    7. 5.7  Analog/Digital IO
      1. 5.7.1  Electrical Characteristics
      2. 5.7.2 Switching Characteristics
    8. 5.8  ADC
      1. 5.8.1 Electrical Characteristics
      2. 5.8.2 Linearity Parameters
      3. 5.8.3 Switching Characteristics
    9. 5.9  VREF
      1. 5.9.1 Electrical Characteristics
      2. 5.9.2 Voltage Characteristics
    10. 5.10 I2C
      1. 5.10.1 I2C Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Multiplexer
      2. 6.3.2 Voltage Reference
      3. 6.3.3 Oscillator
      4. 6.3.4 Output Data Rate and Conversion Time
      5. 6.3.5 Digital Comparator
      6. 6.3.6 Conversion Ready Pin
      7. 6.3.7 Interrupt Output (INT)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset and Power-Up
      2. 6.4.2 Operating Modes
        1. 6.4.2.1 Single-Shot Mode
        2. 6.4.2.2 Continuous-Conversion Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 I2C Address Selection
        2. 6.5.1.2 I2C General Call
        3. 6.5.1.3 I2C Speed Modes
      2. 6.5.2 Target Mode Operations
        1. 6.5.2.1 Receive Mode
        2. 6.5.2.2 Transmit Mode
      3. 6.5.3 Writing To and Reading From the Registers
      4. 6.5.4 Data Format
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Schematic
      2. 8.1.2 ADC Configuration Examples
      3. 8.1.3 GPIO Configuration Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.7 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. Resetting the interrupt output is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os (if they are set up as digital) after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as a digital output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pull-up resistor to VCC, depending on the application. INT should be connected to the voltage source of the device that requires the interrupt information.