SPVA044A June   2026  â€“ June 2026 AM2432 , AM2754-Q1 , AM625 , AM62A7 , AM62D-Q1 , AM62L , AM62P , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Terminology
  6. 3Methodology
  7. 4Benchmarking Flash Operations
    1. 4.1 Processor - AM243x / AM64x
      1. 4.1.1 TMDS243EVM / TMDS64EVM
      2. 4.1.2 LP-AM243
    2. 4.2 Processor - AM275x
      1. 4.2.1 AUDIO-AM275-EVM
    3. 4.3 Processor - AM62x
      1. 4.3.1 SK-AM62
    4. 4.4 Processor - AM62Ax
      1. 4.4.1 SK-AM62A-LP
  8. 5Observations and Conclusions
  9. 6Summary
  10. 7References

LP-AM243

CoreR5F
BoardLP-AM243
FlashNOR QSPI S25HL512T
Input Clock Frequency100 MHz
Input Clock Divider4
Protocol4S-4D-4D

Theoretical throughput for DAC Reads: 100MiBps

Average throughput observed for DAC Reads: 94.78MiBps

Table 4-3 4S-4D-4D on R5F Core
FrequencyDividerData Size UsedDMAPHYThroughput (MiBps)
INDAC WritesDAC ReadsDAC Reads with failed OTP ValidationINDAC ReadsErase
100MHz41KiBNoNo0.400.67N/A21.070.001
NoYes0.401.570.002N/A0.001
YesNo0.400.67N/AN/A0.001
YesYes0.401.570.002N/A0.001
10KiBNoNo0.430.67N/A24.500.01
NoYes0.431.580.02N/A0.01
YesNo0.4323.86N/AN/A0.01
YesYes0.4382.850.02N/A0.01
256KiBNoNo0.430.67N/A24.660.30
NoYes0.431.580.40N/A0.30
YesNo0.4324.65N/AN/A0.30
YesYes0.4394.500.40N/A0.30
512KiBNoNo0.430.67N/A24.670.31
NoYes0.431.580.78N/A0.31
YesNo0.4324.67N/AN/A0.31
YesYes0.4394.830.78N/A0.31
1MiBNoNo0.430.67N/A24.670.31
NoYes0.431.581.56N/A0.31
YesNo0.4324.67N/AN/A0.31
YesYes0.4394.861.56N/A0.31
5MiBNoNo0.430.67N/A24.670.31
NoYes0.431.587.30N/A0.31
YesNo0.4324.67N/AN/A0.31
YesYes0.4394.867.30N/A0.31
10MiBNoNo0.430.67N/A24.670.31
NoYes0.431.5813.56N/A0.31
YesNo0.4324.67N/AN/A0.31
YesYes0.4394.8713.56N/A0.31