SSZTB85 june 2016 LMX2592 , LMX8410L , TRF370315 , TRF370317 , TRF370333 , TRF370417 , TRF3705 , TRF3710 , TRF371109 , TRF371125 , TRF371135 , TRF372017 , TRF3722 , TRF37T05

As one of the most critical design
parameters, the choice of loop bandwidth involves trade-offs between jitter, phase
noise, lock time and spurs. The loop bandwidth that is optimal for jitter,
BW_{JIT}, can often be the best choice for many clocking applications,
such as data converter clocking. In cases where BW_{JIT} is not the best
choice, starting there is still the first step to finding the optimal loop
bandwidth.

In Figure 1, the offset where the phase-locked loop (PLL) and voltage-controlled
oscillator (VCO) noise cross, BW_{JIT} (about 140kHz) optimizes jitter by
minimizing the area under the curve.

Although this bandwidth,
BW_{JIT}, is optimal for jitter, it is not for phase noise, lock time
and spurs. Figure 2
gives a relative idea of the impact of loop bandwidth on these performance
metrics.

To illustrate Figure 2, consider the simulation in Figure 3, which shows the effect of varying the loop bandwidth. The lock time and jitter-normalized metrics are the percentage increase from the lowest value shown in Figure 3. The spur and phase-noise metrics are the decibel increase from the lowest value shown in Figure 3.

As Figure 1 predicted, the optimal jitter is indeed best for a loop bandwidth around 140kHz. Increasing the loop bandwidth beyond this benefits lock time and 10kHz phase noise, but degrades the spur and phase noise at 1MHz offset.

Thus, a good approach to choosing loop
bandwidth might be to choose the optimal jitter bandwidth (BW_{JIT}) as a
starting point, then increase to improve lock time or close in phase noise, or
decrease to improve far-out phase noise or spurs.

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