5 Synchronous PWM Pulse Generation

As mentioned earlier, an OPP waveform can require a higher of compare events, or edges, within a PWM period. F29 MCU's Type 5 ePWM module with its XCMP feature enables OPP by supporting multiple compare events per PWM period. Figure 5-1 demonstrates 4 XCMP events, or 4 edges, within a single PWM period. Without this feature, competitor MCUs are limited to fewer independent edges within a PWM period, limiting their ability to run OPP especially at lower speeds – leaving efficiency gains on the table.

Accurate edge placement is also a critical factor for Synchronous PWM pulse generation. The slightest error on PWM edge placement results in motor harmonic losses. The key differentiators on F29 MCUs that solve this problem are twofold:

• C29 performance which addresses the high demand for calculations on how many edges need to be placed, and exactly when.
• Tight CPU to PWM interconnect: with minimal CPU cycles needed to update PWM

Because the CPU must write to the PWM register at every compare event, it can take significant CPU bandwidth if there are multiple edges in a single PWM period. But thanks to the ultra-low latency of the C29 CPU to the PWM interconnect, there are minimal CPU cycles needed to keep up with the demand of PWM compare events. This effectively resolves the concern of CPU bandwidth loss due to several PWM register writes.