1 SST Design Challenges

Designing such a complex system can present some challenges when improving upon the conventional transformer architecture.

A key benefit of SSTs over conventional transformers is power efficiency. However, efficiency is tied to faster switching frequency. To achieve this, the data that controls the switching needs to be sent faster. In addition, this data would need to pass through a series of blocks if operating in a daisy chain. Device latency becomes a factor as data would need to move through the entire chain to get to all necessary cells.

Another key benefit of SSTs over conventional transformers is increased power density. SSTs realize this benefit from a reduced transformer size due to faster frequency across the transformer loosening the requirements on the size due to Lorentz Law. In addition, technological developments have pushed the introduction of a single stage AC converter. This simplifies the AC-DC-AC converter into a single stage (such as a matrix converter) where the incoming signal is manipulated and sped up without intermediate rectification. With this simplification, more data must be transmitted through the MV MCU to verify proper operation of the single-stage circuit. This data must be sent within an amount of time to still adhere to the control loop bandwidth of the MV stage. In addition, as switching becomes even faster, verifying synchronization across cells are important to make sure that there are no contentions on the output.

Overall, there is a growing need for faster, more deterministic communication to enable for more power efficient, spatially dense SST modules.