There are two types of ethernet that TI offers – standard ethernet and single pair ethernet. Standard ethernet supports up to 100m cabling at fixed speeds of 10Mbps, 100Mbps, and 1Gbps. This is using CAT5e or CAT6 cabling where there are either two or four twisted pairs used for communication. Single pair ethernet has similar speeds but is more fixed (1 speed per device, vs multispeed on the standard ethernet devices) and lowers the cable type to a single twisted pair for communication. However, there is a trade-off of lower cable lengths due to serialization and bidirectional communication leading to differences in the analog and digital circuitry.

For 10/100Mbps standard ethernet, DP83822xF and DP83826A will be best suited for this application. DP83826A is recommended if the lowest deterministic latency (dozens of nanoseconds) is required along with the strictest EMC testing for a module. DP83822xF is Texas Instruments' 100BASE-FX design for the MV optical connections. For 1Gbps standard ethernet, DP83869HM is best suited with copper and fiber support in both 100Mbps and 1Gbps speeds. Texas Instruments also has a 50kW SST reference design available, TIDA-011012 which utilizes a single daisy copper daisy chain with DP83826, with localized fiber connections between the LV and MV control board. This allows for 10/100Mbps data throughput on the communication loop with two PHYs per LV board.

Texas Instruments also offers Single Pair Ethernet (SPE) PHY transceivers in 10Mbps, 100Mbps, and 1Gbps. SPE allows for lighter cabling, thereby reducing cost and weight of the SST while still maintaining fast speeds and hundreds of nanoseconds of latency. For 100Mbps, DP83TC817S-Q1 is the best suited PHY for this application while for 1Gbps, DP83TG721x-Q1 will be recommended. Like standard ethernet, these devices use point to point connections which work best in a daisy chain for a control loop. Texas Instruments also offers multidrop 10Mbps PHYs which follow 10BASE-T1S. Adopting T1S ethernet in an SST provides a direct upgrade over CAN, LIN, and RS-485 due to faster speeds while maintaining the existing cabling architecture if upgrading from the latter technologies. For a pure transceiver, DP83TD53x-Q1 is an analog front end (AFE) device with OA-3 pin for digital communication to a SoC. DP83TD555J-Q1 is an enhanced T1S device which integrates the AFE alongside a Physical Layer Collision Avoidance (PLCA) layer, PHY Control layer, Media Access Control layer, and SPI receiver to easily interface T1S communication with SPI-compatible SoC's.