SWRS350A December   2025  – June 2026 IWRL6432WMOD

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Terminal Configurations and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Module Power Management
    5. 5.5  Typical Power Consumption Numbers
    6. 5.6  Peak Current Requirement per Voltage Rail
    7. 5.7  RF Specification
    8. 5.8  Antenna Position
      1. 5.8.1 2D Antenna Array With 3D Detection Capability
    9. 5.9  Antenna Gain Plot
      1. 5.9.1 Measured Azimuth Loopback Plot
      2. 5.9.2 Measured Elevation Loopback Plot
    10. 5.10 Thermal Resistance Characteristics
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1 Power Supply Sequencing and Reset Timing
      2. 5.11.2 MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 5.11.2.1 SPI Timing Conditions
        2. 5.11.2.2 SPI—Peripheral Mode
          1. 5.11.2.2.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 5.11.2.2.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
        3. 5.11.2.3 SPI Protocol
          1. 5.11.2.3.1 Data Format for Host Communication over SPI
          2. 5.11.2.3.2 Typical Sequence Diagram
      3. 5.11.3 Dedicated Input/Output
        1. 5.11.3.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      4. 5.11.4 Serial Communication Interface (SCI)
        1. 5.11.4.1 SCI Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Module Images
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 Host Interface
        1. 6.3.1.1 Interface Signal Description
        2. 6.3.1.2 Operating Modes
      2. 6.3.2 Device Firmware
  8. 7 Device Certification
    1. 7.1 FCC Certification and Statement
    2. 7.2 ETSI/CE
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Autonomous Mode
        2. 8.1.1.2 Secondary Device Mode
    2. 8.2 Test Results
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Device Marking
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Reflow Information
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
5.11.2.2.1 Timing and Switching Requirements for SPI - Peripheral Mode
Table 5-5 and Table 5-6 present timing requirements for SPI -Peripheral Mode.
Table 5-5 SPI Timing Requirements - Peripheral Mode
NO.(1)(3) PARAMETER DESCRIPTION MIN MAX UNIT
SS1 tc(SPICLK) Cycle time, SPI_CLK 24.6 ns
SS2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45*P2 ns
SS3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45*P2 ns
SS4 tsu(SIMO-SPICLK) Setup time, SPI_D[x] valid before SPI_CLK active edge

3

 ns
SS5 th(SPICLK-SIMO) Hold time, SPI_D[x] valid after SPI_CLK active edge

1

 ns
SS8 tsu(CS-SPICLK) Setup time, SPI_CS[x] valid before SPI_CLK first edge 5 ns
SS9 th(SPICLK-CS) Hold time, SPI_CS[x] valid after SPI_CLK last edge 5 ns

SS10

sr

Input Slew Rate for all pins

1

3

ns

SS11

Cb

Capacitive load on D0 and D1

2

15

pF
Table 5-6 SPI Switching Characteristics Peripheral Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SS6 td(SPICLK-SOMI) Delay time, SPI_CLK active edge to McSPI_somi transition 0

5.77

 ns
SS7 tsk(CS-SOMI) Delay time, SPI_CS[x] active edge to McSPI_somi transition

5.77

 ns
  1. P = This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
  2. P = SPICLK period.
  3. PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.