SWRS350A December   2025  – June 2026 IWRL6432WMOD

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Terminal Configurations and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Module Power Management
    5. 5.5  Typical Power Consumption Numbers
    6. 5.6  Peak Current Requirement per Voltage Rail
    7. 5.7  RF Specification
    8. 5.8  Antenna Position
      1. 5.8.1 2D Antenna Array With 3D Detection Capability
    9. 5.9  Antenna Gain Plot
      1. 5.9.1 Measured Azimuth Loopback Plot
      2. 5.9.2 Measured Elevation Loopback Plot
    10. 5.10 Thermal Resistance Characteristics
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1 Power Supply Sequencing and Reset Timing
      2. 5.11.2 MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 5.11.2.1 SPI Timing Conditions
        2. 5.11.2.2 SPI—Peripheral Mode
          1. 5.11.2.2.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 5.11.2.2.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
        3. 5.11.2.3 SPI Protocol
          1. 5.11.2.3.1 Data Format for Host Communication over SPI
          2. 5.11.2.3.2 Typical Sequence Diagram
      3. 5.11.3 Dedicated Input/Output
        1. 5.11.3.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      4. 5.11.4 Serial Communication Interface (SCI)
        1. 5.11.4.1 SCI Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Module Images
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 Host Interface
        1. 6.3.1.1 Interface Signal Description
        2. 6.3.1.2 Operating Modes
      2. 6.3.2 Device Firmware
  8. 7 Device Certification
    1. 7.1 FCC Certification and Statement
    2. 7.2 ETSI/CE
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Autonomous Mode
        2. 8.1.1.2 Secondary Device Mode
    2. 8.2 Test Results
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Device Marking
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Reflow Information
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.1.1 Interface Signal Description

The IWRL6432WMOD communicates with an external host MCU through a set of dedicated hardware signals. The primary data path is a synchronous SPI bus. Additional GPIO signals coordinate power state and interrupt-driven communication flow.

Signal Direction (from HOST) Type Description
SPI (MOSI/MISO/SCLK/CS) Bidirectional SPI Bus Primary synchronous serial interface. Host MCU is SPI Controller; IWRL6432WMOD is SPI Peripheral.
SPI_BUSY Input to Host GPIO — Output from Module Active HIGH. Asserted by the module when it is processing a command and cannot accept new SPI transactions. Host must poll or interrupt on this before initiating transfers.
PRESENCE_DETECT Input to Host GPIO — Output from Module In Autonomous and Multi-Zone modes: HIGH indicates Presence detected. In Verbose mode: toggles to indicate End-of-Frame, allowing host to synchronize data reads.
WAKE_UP Output from Host GPIO — Input to Module Active HIGH. Host must assert before any SPI API transaction and de-assert after the transaction completes. Prevents the module from entering Deep Sleep during communication. The WAKE_UP (Module Wakeup Input) should be pulled LOW using pull down resistor (lower than 10KOhm) on customer hardware.
nRESET Output from Host GPIO — Input to Module Active LOW. Host releases (de-asserts) this signal to power on the module. Must remain HIGH during normal operation.
Note: SPI_BUSY must be checked for LOW before asserting CS and beginning any SPI transfer. Initiating a transfer while SPI_BUSY is HIGH may corrupt the transaction and cause undefined module behavior.