SWRS350B December   2025  – September 2026 IWRL6432WMOD

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Terminal Configurations and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Module Power Management
    5. 5.5  Typical Power Consumption Numbers
    6. 5.6  Peak Current Requirement per Voltage Rail
    7. 5.7  RF Specification
    8. 5.8  Antenna Position
      1. 5.8.1 2D Antenna Array With 3D Detection Capability
    9. 5.9  Antenna Gain Plot
      1. 5.9.1 Measured Azimuth Loopback Plot
      2. 5.9.2 Measured Elevation Loopback Plot
    10. 5.10 Thermal Resistance Characteristics
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1 Power Supply Sequencing and Reset Timing
      2. 5.11.2 MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 5.11.2.1 SPI Timing Conditions
        2. 5.11.2.2 SPI—Peripheral Mode
          1. 5.11.2.2.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 5.11.2.2.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
        3. 5.11.2.3 SPI Protocol
          1. 5.11.2.3.1 Data Format for Host Communication over SPI
          2. 5.11.2.3.2 Typical Sequence Diagram
      3. 5.11.3 Dedicated Input/Output
        1. 5.11.3.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      4. 5.11.4 Serial Communication Interface (SCI)
        1. 5.11.4.1 SCI Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Module Images
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 Host Interface
        1. 6.3.1.1 Interface Signal Description
        2. 6.3.1.2 Operating Modes
      2. 6.3.2 Device Firmware
  8. 7 Device Certification
    1. 7.1 FCC Certification and Statement
    2. 7.2 ETSI/CE
    3. 7.3 End Product Labeling
    4. 7.4 Manual Information to the End User
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Autonomous Mode
        2. 8.1.1.2 Secondary Device Mode
    2. 8.2 Test Results
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Device Marking
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Reflow Information
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4.2 Signal Descriptions

Note: All digital IO pins of the device (except NRESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.
Table 4-1 Power Supply Signal Descriptions
SIGNAL NAME DESCRIPTION PIN TYPE PIN
VCC 3.3V Supply PWR 7, 8
VIOIN 3.3V supply PWR 29
GND GND GND 5, 6, 25, 27, 28, 30
SPI BUSY Host interrupt / SPI host clock request signal O 1
SPI MOSI SPI MOSI I 21
SPI MISO SPI MISO O 18
SPI CLK SPI Clock I 20
SPI CS SPI Chip Select I 19
UART TX(1) UART Transmit Data O 13
UART RX(1) UART Receive Data I 12
SOP0 Sense On Power A 10
NRESET NRESET input A 15
Presence Indication Output

Output for presence indication in the Region Of Interest

 O 2
Module Wake Up Input Input signal to wakeup the IWRL6432W I 3
NC No Connnection - 4, 9, 11, 14, 16, 17, 22, 23, 24, 26

  1. For uDFP patch updates only. This is not the application interface.