SWRU437B September   2015  – June 2020 WL1801MOD , WL1805MOD , WL1807MOD , WL1831MOD , WL1835MOD , WL1837MOD

 

  1.   WiLink Module Hardware Integration Guide
    1.     Trademarks
    2. 1  Module Variant Table
      1. 1.1 WiLink WLAN Antenna Configuration
        1. 1.1.1 Single-Input Single-Output (SISO)
        2. 1.1.2 Multiple-Input Multiple-Output (MIMO)/Maximum Ratio Combining (MRC)
    3. 2  Critical Connections
    4. 3  Power Supply
      1. 3.1 Power Up/Shutdown Sequence
        1. 3.1.1 Power Up
        2. 3.1.2 Shutdown
      2. 3.2 Power Sequencing
    5. 4  Clocks
      1. 4.1 Slow Clock
      2. 4.2 Fast Clock
    6. 5  Current Consumption
      1. 5.1 Performance Parameters - Typical
    7. 6  Antenna
    8. 7  Ground Connections
    9. 8  Layout
    10. 9  Hardware Troubleshoot
      1. 9.1 System Requirements
      2. 9.2 Power Rails
      3. 9.3 Critcal Supplies
      4. 9.4 Sense on Reset
      5. 9.5 WLAN
        1. 9.5.1 WLAN Host Interface (SDIO)
        2. 9.5.2 WLAN IRQ Operation (SDIO Out-of-Band Interrupt)
      6. 9.6 Bluetooth and Bluetooth Low Energy
        1. 9.6.1 Bluetooth UART HCI Interface
        2. 9.6.2 Bluetooth PCM
      7. 9.7 Reserved Pins
      8. 9.8 Debug
    11. 10 WiFi_Zigbee Coex
    12. 11 References
  2.   Revision History

9.6.2 Bluetooth PCM

There are two lines that can be bidirectional (CLK/FSYNC) to support master and slave configuration and two directional pins: AUD_OUT (output) and AUD_IN (input).

All four lines should be connected to the HOST PCM interface.

bt_pcm.gifFigure 10. HOST PCM Interface

In case the PCM interface is not used, leave not connected (N.C.).

Table 9. PCM Interface Lines

Pin Number Name Type Description
56 BT_AUD_IN I Bluetooth PCM data output
57 BT_AUD_OUT O Bluetooth PCM data output
58 BT_AUD_FSYNC I/O Bluetooth PCM frame sync input or output
60 BT_AUD_CLK I/O Bluetooth PCM clock input or output