SWRU612 December   2023 CC3300 , CC3301 , CC3351

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Power-Up Sequence
        1. 2.2.2.1 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram - Default Speed
        2. 2.5.2.2 SDIO Timing Diagram - High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 Coexistence
  6. 3Layout Considerations
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design Layout
      2. 3.1.2 BP-CC3301 Design Layout
      3. 3.1.3 M2-CC3301 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO

2.2.2 Power-Up Sequence

A crucial point of CC33xx device integration is that proper power-up and power-down sequences must be followed to avoid damage to the device.

  • VDD_MAIN_IN and VIO must be supplied from the same source to prevent glitches on the IO during power up.
  • VDDA_IN1/IN2 and PA_LDO_IN can be supplied independently of all other supplies.
  • All supplies (VDD_MAIN_IN, VIO, VDDA_IN1/2, and PA_LDO_IN) must be available before Reset is deasserted (high).
  • Reset pin should be held low for ~10 μs after stabilization of all external power supplies.
  • When having an external slow clock, ensure that the clock is stable before Reset is deasserted (high).