SWRU612 December   2023 CC3300 , CC3300MOD , CC3301 , CC3301MOD , CC3351 , CC3351MOD

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Power-Up Sequence
        1. 2.2.2.1 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram - Default Speed
        2. 2.5.2.2 SDIO Timing Diagram - High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 Coexistence
  6. 3Layout Considerations
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design Layout
      2. 3.1.2 BP-CC3301 Design Layout
      3. 3.1.3 M2-CC3301 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO

2.5.2.1 SDIO Timing Diagram - Default Speed

GUID-8E24678B-EA1F-4852-81BF-FFDD893B26B4-low.png Figure 2-3 SDIO Default Input Timing
GUID-BA1659A0-57C3-44A3-B64C-DB41B2C253C4-low.png Figure 2-4 SDIO Default Output Timing
Table 2-5 SDIO Timing Parameters - Default Speed
Parameter Description MIN MAX Unit
fclock Clock frequency, CLK 26 MHz
tHigh High Period 10 ns
tLow Low Period 10
tTLH Rise time, CLK 10
tTHL Fall time, CLK 10
tISU Setup time, input valid before CLK ↑ 5
tIH Hold time, input valid after CLK ↑ 5
tODLY Delay time, CLK ↓ to output valid 2 14
CL Capacitive load on outputs 15
40

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