Revisions Affected

B

Details

UART issues a μDMA burst write request when the number of entries in the FIFO is less than or equal to the configured burst FIFO threshold. A subsequent μDMA write burst request is issued, if the total FIFO entries are still below the configured threshold. UART takes one additional SVT clock cycle to update the internal FIFO level, when compared to μDMA signaling an end to its burst active state. In corner cases, dependent on initial UART FIFO level, configured FIFO threshold for burst request, interconnect latencies, and so on, this additional clock latency within UART can cause a spurious write burst request to be generated towards μDMA, which might cause the last write(s) by μDMA responding to this to get missed. This is not seen on UART read burst requests as μDMA waits for the read to complete before signaling an end of read burst.

Workaround

When used along with UART, μDMA SETBURST must be configured for burst requests.

μDMA arbitration size must be 2.

TX FIFO level trigger must be set to ≤ 1/4 empty for the write burst trigger