TIDUEY0A November 2020 – December 2025
Use the setup in Section 3.3.3 to test the current load regulation.
| FSR (A) | 10 | |||||||
|---|---|---|---|---|---|---|---|---|
| OUTPUT MODE | CHARGING | DISCHARGING | ||||||
| ISET (A) | 0.1 | 1 | 5 | 10 | 0.1 | 1 | 5 | 10 |
| E-LOAD CV MODE | TERMINAL VOLTAGE READING | |||||||
| VSET(V) | Iactual (A) | Iactual (A) | Iactual (A) | Iactual (A) | Iactual (A) | Iactual (A) | Iactual (A) | Iactual (A) |
| 1 | 0.0996 | 0.9998 | 4.99993 | 10.0005 | –0.1005 | –1.0001 | –5.001 | –10.001 |
| 2 | 0.0995 | 0.9996 | 4.99995 | 10.0008 | –0.1002 | –1.00025 | –5.0011 | –10.001 |
| 3 | 0.09985 | 0.9995 | 4.99995 | 10.0008 | –0.1005 | –1.0002 | –5.001 | –10.0008 |
| 4 | 0.09925 | 0.9995 | 4.99995 | 10.0008 | –0.1005 | –1.0002 | –5.001 | –10.0011 |
| Error (mA) | 0.7500 | 0.5 | 0.05 | –0.8 | –0.5 | –0.25 | –1.1 | –1.1 |
| Error (%FSR) | 0.0075 | 0.0050 | 0.0005 | 0.0080 | 0.0050 | 0.0025 | 0.0110 | 0.0110 |