TIDA-010191

Space-grade multichannel JESD204B 15-GHz clocking reference design

TIDA-010191

Design files

Overview

Phased-array antennas and digital beamforming are key technologies that will boost the performance of future spaceborne radar imaging and broadband satellite communication systems. Digital beamforming, unlike analog beamforming, typically requires a set of data converters per antenna element. These converters need clocks with a specific defined phase relationship. This reference design shows how to generate low noise megahertz to gigahertz clock signals with defined and adjustable phase relationship. Clock phase even recovery is possible after single event strikes. JESD204B support is shown by operating two ADC12DJ3200QML-SP evaluation modules with their corresponding FPGA-based capturing platforms at 3.2 GHz with 10-ps board-to-board skew.

Features
  • Multichannel JESD204B-compliant clock tree
  • Up to 15-GHz sample clock generation
  • Less than 10-ps clock skew between channels
  • Low phase noise (< 100 fs) clock signal
  • Radiation hardened high-speed ADC, clocking, RF amplifiers and point-of-load power devices
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

PDF | HTML
TIDUEY8.PDF (3133 K)

Reference design overview and verified performance test data

TIDMBE8.PDF (3830 K)

Detailed schematic diagram for design layout and components

TIDMBE9.PDF (207 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDMBF0.PDF (1671 K)

Detailed overview of design layout for component placement

TIDMBF2.ZIP (13862 K)

Files used for 3D models or 2D drawings of IC components

TIDCGD9.ZIP (18422 K)

Design file that contains information on physical board layer of design PCB

TIDMBF1.ZIP (13691 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

Clock jitter cleaners & synchronizers

LMK04832-SPRadiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner

Data sheet: PDF | HTML
Analog current-sense amplifiers

INA901-SPRadiation hardened, -15-V to 65-V, split-stage current sense amplifier with in-line filter option

Data sheet: PDF | HTML
Buck converters (integrated switch)

TPS50601A-SPRadiation-hardened QMLV, 3-V to 7-V input, 6-A synchronous step-down converter

Data sheet: PDF | HTML
Clock buffers

CDCLVP111-SP1:10 high speed clock buffer with selectable input clock driver

Data sheet: PDF | HTML
Digital temperature sensors

TMP461-SPRadiation-hardness-assured (RHA), high-accuracy remote and local temperature sensor

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A4501-SPRadiation-hardened, QMLV, 1.5-V to 20-V input 1.5-A low-dropout (LDO) regulator

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7H1101A-SPRadiation-hardened QMLV, 1.5-V to 7-V input, 3-A low-noise adjustable low-dropout (LDO) regulator

Data sheet: PDF | HTML
RF FDAs

LMH5401-SPRadiation Hardness Assured (RHA) 6.5GHz Ultra Wideband Fully Differential Amplifier

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX2615-SPSpace grade 40-MHz to 15-GHz wideband synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML
eFuses & hot swap controllers

TPS7H2201-SPRadiation-hardened, QMLV and QMLP 1.5-V to 7-V input 6-A eFuse

Data sheet: PDF | HTML

Technical documentation

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* Design guide Space-Grade, Multichannel, JESD204B 15-GHz Clock Reference Design PDF | HTML Mar. 21, 2023

Related design resources

Reference designs

REFERENCE DESIGN
TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01022 Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers TIDA-01024 High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

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