SCLS738C September   2013  – June 2022 SN74LV1T04

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Operating Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clamp Diode Structure
      2. 9.3.2 Balanced CMOS Push-Pull Outputs
    4. 9.4 LVxT Enhanced Input Voltage
      1. 9.4.1 Down Translation
      2. 9.4.2 Up Translation
    5. 9.5 Device Functional Modes
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Single-supply voltage translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating range of 1.8 V to 5.5 V
  • Up translation:
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down translation:
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic output is referenced to VCC
  • Output drive:
    • 8 mA output drive at 5 V
    • 7 mA output drive at 3.3 V
    • 3 mA output drive at 1.8 V
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5 V tolerance on input pins
  • –40°C to +125°C operating temperature range
  • Pb-free packages available: SC-70 (DCK)
    • 2 × 2.1 × 0.65 mm (Height 1.10 mm)
  • Latch-up performance exceeds 250 mA
    per JESD 17
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)
1. See the VIH/VIL and output drive for lower VCC condition.