ADC12QJ1600-SP

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CFCBGA (ALR) 144
  • Radiation Performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 57.4 dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –147 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 1.9W
  • Power supplies: 1.1 V, 1.9 V
  • Radiation Performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 57.4 dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –147 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 1.9W
  • Power supplies: 1.1 V, 1.9 V

ADC12QJ1600-SP is a quad channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.

ADC12QJ1600-SP is a quad channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.

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Similar products you might be interested in

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Pin-for-pin with same functionality to the compared device.
ADC12QJ1600 ACTIVE Quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator The industrial ADC12QJ1600 is pin-for-pin with the -Q1, -SP and -EP versions.
NEW ADC12QJ1600-EP PREVIEW Enhanced-product, quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface ADC12QJ1600-EP is an excellent prototyping option for the ADC12QJ1600-SP. Same pinout and build materials.
ADC12QJ1600-Q1 ACTIVE Automotive, quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface The automotive ADC12QJ1600-Q1 is pin-for-pin with the -SP and -EP versions.

Technical documentation

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* Data sheet ADC12QJ1600-SP Quad Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet PDF | HTML 19 Jan 2022
Technical article How SHP in plastic packaging addresses 3 key space application design challenges 17 Oct 2022

Design & development

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Evaluation board

ADC12QJ1600EVM — ADC12QJ1600 evaluation module for quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface

The ADC12QJ1600 evaluation module (EVM) allows for the evaluation of the ADC12QJ1600-Q1 product. ADC12QJ1600-Q1 is a low-power, 12-bit, quad-channel, 1.6-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which (...)

User guide: PDF
Not available on TI.com
Evaluation board

TSW12QJ1600EVM — ADC12QJ1600-Q1 8-ch (two synchronized 4-ch) 12-bit 1.6-GSPS JESD204C interface ADC evaluation module

The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.

This design (...)

User guide: PDF
Not available on TI.com
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCCSP (ALR) 144 View options

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