ADC12QJ1600-Q1

• AEC-Q100 qualified for automotive applications:
  • Temperature grade 1: –40°C to +125°C, T_A
• ADC Core:
  • Resolution: 12 Bit
  • Maximum sampling rate: 1.6 GSPS
  • Non-interleaved architecture
  • Internal dither reduces high-order harmonics
• Performance specifications (–1 dBFS):
  • SNR (100 MHz): 57.4 dBFS
  • ENOB (100 MHz): 9.1 Bits
  • SFDR (100 MHz): 64 dBc
  • Noise floor (–20 dBFS): –147 dBFS
• Full-scale input voltage: 800 mV_PP-DIFF
• Full-power input bandwidth: 6 GHz
• JESD204C Serial data interface:
  • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
  • Maximum baud-rate: 17.16 Gbps
  • 64B/66B and 8B/10B encoding modes
  • Subclass-1 support for deterministic latency
  • Compatible with JESD204B receivers
• Optional internal sampling clock generation
  • Internal PLL and VCO (7.2–8.2 GHz)
• SYSREF Windowing eases synchronization
• Four clock outputs simplify system clocking
  • Reference clocks for FPGA or adjacent ADC
  • Reference clock for SerDes transceivers
• Timestamp input and output for pulsed systems
• Power consumption (1 GSPS):
  • Quad Channel: 477 mW / channel
  • Dual channel: 700 mW / channel
  • Single channel: 1000 mW
• Power supplies: 1.1 V, 1.9 V

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ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.