Packaging information
| Package | Pins VQFN (RGE) | 24 |
| Operating temperature range (°C) -40 to 105 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the CDCE6214
- Configurable high performance, low-power, frac-N
PLL with RMS jitter with spurs (12kHz – 20MHz,
Fout > 100MHz) as:
- Integer mode:
- Differential output: 350fs typical (typ.), 600fs maximum (max)
- LVCMOS output: 1.05ps typ., 1.5ps max
- Fractional mode:
- Differential output: 1.7ps typ., 2.1ps max
- LVCMOS output: 2.0ps typ., 4.0ps max
- Integer mode:
- Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5/6 without SSC
- Typ. power consumption: 65mA for 4-output channel, 23mA for 1-output channel.
- Universal clock input
- Differential AC-coupled or LVCMOS: 10MHz to 200MHz
- Crystal: 10MHz to 50MHz
- Flexible output clock distribution
- Four channel dividers: Up to five unique output frequencies from 24kHz to 328.125MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
- Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
- Fully-integrated, configurable loop bandwidth: 100kHz to 1.6MHz
- Single or mixed supply for level translation: 1.8V, 2.5V, 3.3V
- Configurable GPIOs and flexible configuration options
- I2C-compatible interface: up to 400kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
- Supports 100Ω systems
- Low electromagnetic emissions
- Small footprint: 24-pin VQFN (4mm × 4mm)
Description for the CDCE6214
The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.
The CDCE6214 can be configured through the I2C interface in fall-back mode only. In the absence of the serial interface, the GPIO pins can be used in pin mode to configure the product into distinctive configurations.
On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.
Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8V, 2.5V, or 3.3V ±5% supply, and output blocks operate from a 1.8V, 2.5V, or 3.3V ±5% supply.
The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant on clocking device with a low power consumption.