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Product details

Parameters

Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 350 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Universal input, LVCMOS and XTAL Output type LVCMOS, LVDS, LVPECL, HCSL Operating temperature range (C) -40 to 85 Features I2C, Pin programmable, Integrated EEPROM, Serial interface Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

VQFN (RGE) 24 16 mm² 4 x 4 open-in-new Find other Clock generators

Features

  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout > 100 MHz) as:
    • Integer mode:
      • Differential output: 350 fs typical, 600 fs maximum
      • LVCMOS output: 1.05 ps typical, 1.5 ps maximum
    • Fractional mode:
      • Differential output: 1.7 ps typical, 2.1 ps maximum
      • LVCMOS output: 2.0 ps typical, 4.0 ps maximum
  • Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
  • 2.335-GHz to 2.625-GHz internal VCO
  • Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
  • Universal clock input, two reference inputs for redundancy
    • Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
    • Crystal: 10 MHz to 50 MHz
  • Flexible output clock distribution
    • 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
  • Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
  • Configurable GPIOs and flexible configuration options
    • I2C-compatible interface: up to 400 kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100-Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4 mm × 4 mm)

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Description

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 4
Type Title Date
* Datasheet CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet Jul. 02, 2020
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical articles Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical articles Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
199
Description
The CDCE6214-Q1 evalution module (EVM) is an evaluation platform for the CDCE6214-Q1 ultra-low power clock generator. This
evaluation module provides an USB-based interface to access the I2C bus to communicate with the CDCE6214-Q1. Pin control mode can set the device in a specific operation mode.
Features
  • Easy to use the EVM to generate up to 4 differential outputs and 1 LVCMOS output with on board XTAL or an external reference clock
  • Accept differential or single-ended clock and XTAL input
  • Device control pins configurable through jumpers
  • Power from USB (default) or external +5 V, using on board LDOs 1.8 (...)

Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGE) 24 View options

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