Product details


Function Transceiver Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3, 5 Signaling rate (Mbps) 100 Input signal TTL, CMOS, LVTTL, LVDS Output signal TTL, LVTTL, LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • LVDS Signaling
  • 3.3V or 5.0V operation
  • Low power CMOS design
  • Balanced Output Impedance
  • Glitch free power up/down (Driver disabled)
  • High Signaling Rate Capacity (above 100 Mbps)
  • Ultra Low Power Dissipation
  • ±1V Common-Mode Range
  • ±100 mV Receiver Sensitivity
  • Product offered in SOIC and TSSOP packages
  • Flow-Through Pin Out
  • Industrial Temperature Range Operation

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

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The DS90LV019 is a Driver/Receiver designed specifically for the high speed low power point-to-point interconnect applications. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. The DS90LV019 features an independent driver and receiver with TTL/CMOS compatibility (DIN and ROUT). The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE#, and ROUT). The device also features a flow-through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver has 3.5 mA output loop current.

The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common-mode noise rejection.

The receiver threshold is ±100 mV over a ±1V common-mode range and translates the low swing differential levels to standard (TTL/CMOS) levels.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet DS90LV019 3.3V or 5V LVDS Driver/Receiver datasheet (Rev. B) May 14, 2004
More literature Die D/S DS90LV019 MDC 3.3V Or 5V Lvds Driver/Receiver Sep. 07, 2012
Application note An Overview of LVDS Technology Oct. 05, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

The DS90LV047-48AEVM is an evaluation module (EVM) designed for performance and functional evaluation of Texas Instruments' DS90LV047A 3-V LVDS quad CMOS differential line driver and DS90LV048A 3-V LVDS CMOS differential line receiver. With this kit, users can quickly evaluate the output (...)
  • DS90LV047A:  Converts single-ended LVCMOS to differential LVDS
  • DS90LV048A:  Converts differential LVDS to single-ended LVCMOS
  • Greater than 400-Mbps (200 MHz) switching rates
  • Single-supply operation:  3.3 V

Design tools & simulation

SNLM060.ZIP (9 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
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  • Qualification summary
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