Product details


Function Deserializer Signal conditioning EQ Input EMI reduction SSCG, Slew Rate Control Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Display SerDes

Package | Pins | Size

WQFN (NKB) 60 81 mm² 9 x 9 open-in-new Find other Display SerDes


  • 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
  • Application Payloads up to 1.2 Gbps
  • AC Coupled Interconnects: STP up to 10 m or
    Coax 20+m
  • 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • Integrated Terminations on Ser and Des
  • AT-SPEED BIST Mode and Reporting Pin
  • Configurable by Pins or I2C Compatible Serial
    Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • >8 kV HBM ESD Rating
    • Supports Spread Spectrum Clocking (SSC) on
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable
    • Random Data Lock; no Reference Clock
    • Adjustable Input Receiver Equalization
    • LOCK (Real Time Link Status) Reporting Pin
    • Selectable Spread Spectrum Clock Generation
      (SSCG) and Output Slew Rate Control (OS) to
      Reduce EMI
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The DS92LV2411 (Serializer) and DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus over FR-4 printed circuit board backplanes, differential or coax cables.

In addition to the 24-bit data bus interface, the DS92LV2411/12 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB888).

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables long distance transmission over lossy cables and backplanes. The DS92LV2412 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” or “hot plug” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability.

The DS92LV2411/12 chipset is programmable though an I2C interface as well as through Pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV2411 is offered in a 48-Pin WQFN and the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial temperature range of –40°C to +85°C.

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Technical documentation

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Type Title Date
* Datasheet DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer datasheet (Rev. E) Feb. 09, 2015
Application notes DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) Apr. 29, 2013
User guides LV24EVK01 Channel Link II Ser/Des Evaluation Kit User Guide Jan. 25, 2012
User guides Channel Link II Design Guide Jan. 21, 2011

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SNLM125.ZIP (146 KB) - IBIS Model
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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