The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS92LX2121/22 10 - 50 MHz DC-Balanced Ch Link III Bi-Directional Control SER/DES datasheet (Rev. J) | Jan 17, 2014 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | Nov 9, 2018 | ||
| Application note | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | Apr 29, 2013 | ||
| User guide | LX21EVK01 Channel Link III Ser/Des Evaluation Kit | Feb 1, 2012 |
For additional terms or required resources, click any title below to view the detail page where available.
The LX21EVK01 is an evaluation kit designed to demonstrate the performance and capabilities of the DS92LX2121 and DS92LX2122 Channel Link III Serializer/Deserializer chipset.
The DS92LX2121 serializer board accepts LVCMOS input signals for the high speed forward channel and provides additional (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
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