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The LMH0056 HD/SD SDI Reclocker with 4:1 Input Multiplexer retimes serial digital video data conforming to the SMPTE 292M and SMPTE 259M (A & C) standards. The LMH0056 operates at serial data rates of 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. The LMH0056 supports DVB-ASI operation at 270 Mbps. The LMH0056 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming.
The LMH0056 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0056 recovers the serial data-rate clock and optionally provides it as an output. The LMH0056 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass and output mute. The serial data inputs, outputs, and serial data-rate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.
The LMH0056 is powered from a single 3.3V supply. Power dissipation is typically 360 mW. The device is housed in a 48-pin WQFN package.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | LMH0056 HD/SD SDI Reclocker with 4:1 Input Multiplexer datasheet (Rev. C) | Apr 15, 2013 | |
| Selection guide | Broadcast and Professional Video Interface Solutions (Rev. E) | PDF | HTML | Apr 5, 2017 | |
| Application note | AN-2145 Power Considerations for SDI Products (Rev. B) | Apr 26, 2013 | ||
| Application note | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | Apr 26, 2013 | ||
| Application note | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | Apr 26, 2013 | ||
| Application note | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | Nov 12, 2009 | ||
| Application note | Reference Clock Loop Through Application | Jan 16, 2009 | ||
| Design guide | Broadcast Video Owner's Manual | Nov 17, 2006 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
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